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1. 发明申请

US20120002573A1 DATA SIGNAL TRANSCEIVER CIRCUITRY FOR PROVIDING SIMULTANEOUS BI-DIRECTIONAL COMMUNICATION VIA A COMMON CONDUCTOR PAIR 有权
标题翻译：数据信号收发器电路，用于通过公共导体对提供同时的双向通信
公开(公告)号：US20120002573A1
公开(公告)日：2012-01-05
申请号：US13045301
申请日：2011-03-10
申请人： Vijaya G. Ceekala , Qingping Zheng , Min Du , Xin Liu , Chandrakumar R. Pathi
发明人： Vijaya G. Ceekala , Qingping Zheng , Min Du , Xin Liu , Chandrakumar R. Pathi
IPC分类号： H04L5/14
CPC分类号： H04L5/1415 , H04L5/1461 , H04L25/0276 , H04L25/0284 , H04L25/0296 , H04L25/0298 , H04L25/4904 , H04L67/12
摘要： Interface circuitry and method for transmitting and receiving downstream and upstream data signals simultaneously via a common conductor pair. The composite signal containing the downstream and upstream data signal components being conveyed by the common conductor pair is isolated, e.g., via signal filtering or buffering, and combined with an appropriately scaled inverse replica of the outgoing upstream data signal to subtract out upstream data signal components and thereby provide the downstream data signal substantially free of any upstream data signal components.
摘要翻译：用于经由公共导体对同时发送和接收下游和上游数据信号的接口电路和方法。包含由公共导体对传送的下游和上游数据信号分量的复合信号例如通过信号滤波或缓冲被隔离，并且与输出上行数据信号的适当缩放的反向副本相结合以减去上行数据信号分量从而提供基本上没有任何上行数据信号分量的下行数据信号。

2. 发明授权

US07564454B1 Methods and displays having a self-calibrating delay line 有权
标题翻译：具有自校准延迟线的方法和显示器
公开(公告)号：US07564454B1
公开(公告)日：2009-07-21
申请号：US11005139
申请日：2004-12-06
申请人： Peter Shing , Xin Liu , Min Du , Qingping Zheng
发明人： Peter Shing , Xin Liu , Min Du , Qingping Zheng
IPC分类号： G06F3/038
CPC分类号： G09G3/3688 , G09G3/2085 , G09G2320/0693
摘要： A driver arrangement for a display includes at least one driver, such as a column driver, and a delay line arrangement coupled to the driver. The delay line arrangement delays a data signal provided to the driver by a delay period selectable from a plurality of possible delay periods. The delay line arrangement includes a calibration module that, when requested, is configured and arranged to adjust a current delay period produced by the delay line arrangement towards a predetermined delay period. Displays can include the driver arrangement to provide self-calibration of the delay line.
摘要翻译：用于显示器的驱动器装置包括至少一个驱动器，例如列驱动器，以及耦合到驱动器的延迟线布置。延迟线布置将提供给驱动器的数据信号延迟可从多个可能的延迟周期中选择的延迟周期。延迟线布置包括校准模块，其在被请求时被配置和布置成将延迟线布置产生的电流延迟周期调整到预定的延迟周期。显示器可以包括驱动器装置以提供延迟线的自校准。

3. 发明授权

US08923166B2 Data signal transceiver circuitry for providing simultaneous bi-directional communication via a common conductor pair 有权
标题翻译：用于通过公共导体对提供同时双向通信的数据信号收发器电路
公开(公告)号：US08923166B2
公开(公告)日：2014-12-30
申请号：US13045301
申请日：2011-03-10
申请人： Vijaya G. Ceekala , Qingping Zheng , Min Du , Xin Liu , Chandrakumar R. Pathi
发明人： Vijaya G. Ceekala , Qingping Zheng , Min Du , Xin Liu , Chandrakumar R. Pathi
IPC分类号： H04B1/56 , H04L25/49 , H04L5/14 , H04L25/02
CPC分类号： H04L5/1415 , H04L5/1461 , H04L25/0276 , H04L25/0284 , H04L25/0296 , H04L25/0298 , H04L25/4904 , H04L67/12
摘要： Interface circuitry and method for transmitting and receiving downstream and upstream data signals simultaneously via a common conductor pair. The composite signal containing the downstream and upstream data signal components being conveyed by the common conductor pair is isolated, e.g., via signal filtering or buffering, and combined with an appropriately scaled inverse replica of the outgoing upstream data signal to subtract out upstream data signal components and thereby provide the downstream data signal substantially free of any upstream data signal components.
摘要翻译：用于经由公共导体对同时发送和接收下游和上游数据信号的接口电路和方法。包含由公共导体对传送的下游和上游数据信号分量的复合信号例如通过信号滤波或缓冲被隔离，并且与输出上行数据信号的适当缩放的反向副本相结合以减去上行数据信号分量从而提供基本上没有任何上行数据信号分量的下行数据信号。

4. 发明申请

US20090147708A1 TIME SHARED BI-DIRECTIONAL SERIAL SIGNALING SYSTEM 有权
标题翻译：时尚双向串行信令系统
公开(公告)号：US20090147708A1
公开(公告)日：2009-06-11
申请号：US11951631
申请日：2007-12-06
申请人： Xin Liu , Qingping Zheng , John Goldie
发明人： Xin Liu , Qingping Zheng , John Goldie
IPC分类号： H04B1/52
CPC分类号： H04L5/22
摘要： A time shared bi-directional serial signaling system providing a differential signal with apparent duplex signal operation for higher and lower bandwidth data signals in a forward direction and another lower bandwidth data signal in a return direction.
摘要翻译：一种时间共享的双向串行信令系统，提供具有视在双工信号操作的差分信号，用于在正向上的较高和较低带宽数据信号以及在返回方向上的另一较低带宽数据信号。

5. 发明授权

US07512193B1 Circuit and method for pre-emphasis in data serialization 有权
标题翻译：数据序列化预加重电路及方法
公开(公告)号：US07512193B1
公开(公告)日：2009-03-31
申请号：US11120726
申请日：2005-05-02
申请人： Peter Shing , Min Du , Xin Liu , Qingping Zheng
发明人： Peter Shing , Min Du , Xin Liu , Qingping Zheng
IPC分类号： H04L25/49
CPC分类号： H04L25/0286 , H04L25/03343
摘要： A circuit for pre-emphasis in data serialization. The circuit has a signal delayline to incrementally delay a serialized signal, producing a delayed serialized signal. The circuit has a one bit generator circuit, which determines the interval between receipt of one bit and a second bit. The one bit generator circuit has a strobe delayline to incrementally delay a strobe signal, producing a delayed strobe signal, a logical gate to compare the delayed strobe signal with a second strobe signal, and a logical component to determine how long the delayed strobe signal was delayed before it matched the second strobe signal. The circuit also has a comparison gate to detect transition points in the serialized signal by comparing the delayed serialized signal with the serialized signal. The circuit also has a current source to provide increased current for the serialized signal at the detected transition points.
摘要翻译：数据串行化预加重电路。电路具有延迟延迟串行化信号的信号延迟线，产生延迟的串行化信号。该电路具有一位发生器电路，其确定接收到一位和第二位之间的间隔。一比特发生器电路具有选通延迟线，用于递增地延迟选通信号，产生延迟的选通信号，逻辑门以比较延迟的选通信号与第二选通信号，以及逻辑分量，以确定延迟的选通信号为多久在匹配第二个选通信号之前被延迟。该电路还具有比较门，以通过将延迟串行化信号与串行化信号进行比较来检测串行化信号中的转换点。该电路还具有电流源，以在检测到的转变点处为串行化信号提供增加的电流。

6. 发明授权

US07746811B2 Time shared bi-directional serial signaling system 有权
标题翻译：时间共享双向串行信令系统
公开(公告)号：US07746811B2
公开(公告)日：2010-06-29
申请号：US11951631
申请日：2007-12-06
申请人： Xin Liu , Qingping Zheng , John Goldie
发明人： Xin Liu , Qingping Zheng , John Goldie
IPC分类号： H04B1/52
CPC分类号： H04L5/22
摘要： A time shared bi-directional serial signaling system providing a differential signal with apparent duplex signal operation for higher and lower bandwidth data signals in a forward direction and another lower bandwidth data signal in a return direction.
摘要翻译：一种时间共享的双向串行信令系统，提供具有视在双工信号操作的差分信号，用于在正向上的较高和较低带宽数据信号以及在返回方向上的另一较低带宽数据信号。

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