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1. 发明授权

US08051232B2 Data storage device performance optimization methods and apparatuses 有权
标题翻译：数据存储设备性能优化方法和设备
公开(公告)号：US08051232B2
公开(公告)日：2011-11-01
申请号：US11821616
申请日：2007-06-25
申请人： Brian M Dees , Amber D. Huffman , R. Scott Tetrick
发明人： Brian M Dees , Amber D. Huffman , R. Scott Tetrick
IPC分类号： G06F13/00
CPC分类号： G06F3/0659 , G06F3/0613 , G06F3/0671 , G06F3/0676 , G06F3/0677
摘要： Methods and apparatuses for identifying types of data streams and communicating stream information to improve performance of data storage devices are disclosed. Method embodiments generally comprise identifying one or more isochronous requests among a plurality of requests which may be issued to a data storage device, assigning a completion deadline an isochronous request, and communicating the isochronous request and completion deadline information to the data storage device. Apparatus embodiments generally comprise a request identifier to identify an isochronous request, a logic module to assign a completion deadline to the isochronous request, and a communication module to communicate the isochronous request and the completion deadline to a data storage device. Alternative apparatus embodiments may include a monitor module to monitor a system process operating in the system and determine if the system process issues isochronous requests. Various embodiments may process asynchronous requests, including prioritized asynchronous requests, with the isochronous requests.
摘要翻译：公开了用于识别数据流类型和通信流信息以提高数据存储设备性能的方法和装置。方法实施例通常包括识别可以发布到数据存储设备的多个请求中的一个或多个同步请求，分配完成期限等时请求，以及将等时请求和完成期限信息传送到数据存储设备。装置实施例通常包括用于标识同步请求的请求标识符，用于向同步请求分配完成期限的逻辑模块，以及将等时请求和完成期限传送到数据存储设备的通信模块。备选设备实施例可以包括监视器模块，用于监视在系统中操作的系统进程并确定系统进程是否发出等时请求。各种实施例可以处理具有等时请求的异步请求，包括优先级异步请求。

2. 发明申请

US20100082904A1 Apparatus and method to harden computer system 有权
标题翻译：硬化计算机系统的装置和方法
公开(公告)号：US20100082904A1
公开(公告)日：2010-04-01
申请号：US12286340
申请日：2008-09-30
申请人： Dale Juenemann , R. Scott Tetrick , Oscar Pinto
发明人： Dale Juenemann , R. Scott Tetrick , Oscar Pinto
IPC分类号： G06F12/08
CPC分类号： G06F12/0868 , G06F12/0871 , G06F2212/222 , G06F2212/282 , G06F2212/461 , G06F2212/463
摘要： In some embodiments, a non-volatile cache memory may include a segmented non-volatile cache memory configured to be located between a system memory and a mass storage device of an electronic system and a controller coupled to the segmented non-volatile cache memory, wherein the controller is configured to control utilization of the segmented non-volatile cache memory. The segmented non-volatile cache memory may include a file cache segment, the file cache segment to store complete files in accordance with a file cache policy, and a block cache segment, the block cache segment to store one or more blocks of one or more files in accordance with a block cache policy, wherein the block cache policy is different from the file cache policy. The controller may be configured to utilize the file cache segment in accordance with information related to the block cache segment and to utilize the block cache segment in accordance with information related to the file cache segment. Other embodiments are disclosed and claimed.
摘要翻译：在一些实施例中，非易失性高速缓存存储器可以包括分配的非易失性高速缓存存储器，其被配置为位于系统存储器和电子系统的大容量存储设备之间，以及耦合到分段的非易失性高速缓冲存储器的控制器，其中控制器被配置为控制分段的非易失性高速缓冲存储器的利用。分段非易失性高速缓冲存储器可以包括文件高速缓存段，文件高速缓存区段以根据文件高速缓存策略来存储完整文件，以及块高速缓存段，块高速缓存段，用于存储一个或多个文件，其中块高速缓存策略与文件高速缓存策略不同。控制器可以被配置为根据与块高速缓存段相关的信息来利用文件高速缓存段，并且根据与文件高速缓存段有关的信息利用块高速缓存段。公开和要求保护其他实施例。

3. 发明授权

US07539812B2 System and method to increase DRAM parallelism 有权
标题翻译：增加DRAM并行性的系统和方法
公开(公告)号：US07539812B2
公开(公告)日：2009-05-26
申请号：US11171804
申请日：2005-06-30
申请人： R. Scott Tetrick
发明人： R. Scott Tetrick
IPC分类号： G06F13/00 , G06F13/28
CPC分类号： G06F13/1605 , G06F13/4243 , G06F13/4256
摘要： A method and apparatus for a multi-ranked memory protocol. In some embodiments an apparatus may include a memory controller (MC), and a plurality of ranked dynamic random access memory (DRAM) devices interfaced with the MC, wherein timing and initiation operations between the MC and the plurality of ranked DRAM devices and between the plurality of ranked DRAM devices is controlled by the MC. In some embodiments, a method may include addressing a request to one of a plurality of ranked DRAM devices, sending the request from a MC interfaced with the plurality of ranked DRAM devices, and propagating the request from the MC through the plurality of ranked DRAM devices to the addressed ranked DRAM device MC, wherein the requests includes data associated therewith.
摘要翻译：一种用于多级存储器协议的方法和装置。在一些实施例中，装置可以包括存储器控制器（MC）和与MC接口的多个排序的动态随机存取存储器（DRAM）装置，其中，MC与多个排序的DRAM装置之间以及多个排序的DRAM器件由MC控制。在一些实施例中，一种方法可以包括向多个排序的DRAM设备之一寻址请求，从与多个排序的DRAM设备接口的MC发送请求，以及通过多个排序的DRAM设备传播来自MC的请求到所寻址的排序DRAM设备MC，其中请求包括与其相关联的数据。

4. 发明申请

US20090077316A1 LOADING DATA FROM A MEMORY CARD 有权
标题翻译：从记忆卡装载数据
公开(公告)号：US20090077316A1
公开(公告)日：2009-03-19
申请号：US11857289
申请日：2007-09-18
申请人： R. Scott Tetrick
发明人： R. Scott Tetrick
IPC分类号： G06F13/28
CPC分类号： G06F13/385 , Y02D10/14 , Y02D10/151
摘要： A memory card detection method comprising detecting insertion of a memory card into a device's card slot; creating a memory card construct in a non-volatile memory storage; copying data from the memory card to the memory card construct; and informing the device that a new memory card has been inserted and may be accessed from the non-volatile memory storage.
摘要翻译：一种存储卡检测方法，包括检测存储卡插入到设备的卡槽中; 在非易失性存储器存储器中创建存储卡构造; 将数据从存储卡复制到存储卡结构; 并且通知设备已经插入了新的存储卡并且可以从非易失性存储器存储器访问该存储卡。

5. 发明授权

US5682512A Use of deferred bus access for address translation in a shared memory clustered computer system 失效
标题翻译：在共享内存集群计算机系统中使用延迟总线访问进行地址转换
公开(公告)号：US5682512A
公开(公告)日：1997-10-28
申请号：US497621
申请日：1995-06-30
申请人： R. Scott Tetrick
发明人： R. Scott Tetrick
IPC分类号： G06F12/02 , G06F15/167 , G06F12/00
CPC分类号： G06F15/167 , G06F12/0284 , Y10S715/974
摘要： In a shared memory computer system, processing nodes are coupled together by way of cluster bridges. A cluster bridge operating according to the present invention intercepts a global access transaction request issued from a processing node and issues a transaction deferral to indicate that the request will be serviced out-of-order. A map of global addresses which correspond to fixed addresses at the node from which the access request was issued is maintained by the cluster bridge. If the address of the global access transaction request corresponds to a fixed address local to the requesting node, the address is translated at cluster bridge and accessed at the local node in order to complete the deferred request.
摘要翻译：在共享存储器计算机系统中，处理节点通过簇桥耦合在一起。根据本发明工作的群集桥拦截从处理节点发出的全局访问事务请求并发出事务延迟以指示该请求将被无序地服务。集群网桥维护与发出访问请求的节点对应的固定地址的全局地址映射。如果全局访问事务请求的地址对应于请求节点本地的固定地址，则该地址将在群集网桥处转换并在本地节点处进行访问，以完成延迟请求。

6. 发明授权

US08219757B2 Apparatus and method for low touch cache management 有权
标题翻译：低触控缓存管理的装置和方法
公开(公告)号：US08219757B2
公开(公告)日：2012-07-10
申请号：US12286460
申请日：2008-09-30
申请人： Glenn Hinton , Dale Juenemann , R. Scott Tetrick
发明人： Glenn Hinton , Dale Juenemann , R. Scott Tetrick
IPC分类号： G06F12/00
CPC分类号： G06F12/0897 , G06F12/0888 , G06F2212/1021 , G06F2212/222
摘要： In some embodiments, a processor-based system includes a processor, a system memory coupled to the processor, a mass storage device, a cache memory located between the system memory and the mass storage device, and code stored on the processor-based system to cause the processor-based system to utilize the cache memory. The code may be configured to cause the processor-based system to preferentially use only a selected size of the cache memory to store cache entries having less than or equal to a selected number of cache hits. Other embodiments are disclosed and claimed.
摘要翻译：在一些实施例中，基于处理器的系统包括处理器，耦合到处理器的系统存储器，大容量存储设备，位于系统存储器和大容量存储设备之间的高速缓冲存储器以及存储在基于处理器的系统上的代码使基于处理器的系统利用高速缓冲存储器。代码可以被配置为使得基于处理器的系统优先仅使用所选大小的高速缓冲存储器来存储具有小于或等于所选数量的高速缓存命中的高速缓存条目。公开和要求保护其他实施例。

7. 发明申请

US20090327584A1 Apparatus and method for multi-level cache utilization 有权
标题翻译：多级缓存利用的装置和方法
公开(公告)号：US20090327584A1
公开(公告)日：2009-12-31
申请号：US12215762
申请日：2008-06-30
申请人： R. Scott Tetrick , Dale Juenemann , Robert Brennan
发明人： R. Scott Tetrick , Dale Juenemann , Robert Brennan
IPC分类号： G06F12/08 , G06F12/02
CPC分类号： G06F12/0897 , G06F12/0866 , G06F2212/222 , G11C2211/5641
摘要： In some embodiments, a non-volatile cache memory may include a multi-level non-volatile cache memory configured to be located between a system memory and a mass storage device of an electronic system and a controller coupled to the multi-level non-volatile cache memory, wherein the controller is configured to control utilization of the multi-level non-volatile cache memory. Other embodiments are disclosed and claimed.
摘要翻译：在一些实施例中，非易失性高速缓存存储器可以包括配置为位于系统存储器和电子系统的大容量存储设备之间的多级非易失性高速缓存存储器，以及耦合到多级非易失性存储器缓存存储器，其中所述控制器被配置为控制所述多级非易失性高速缓冲存储器的利用。公开和要求保护其他实施例。

8. 发明申请

US20090070526A1 USING EXPLICIT DISK BLOCK CACHEABILITY ATTRIBUTES TO ENHANCE I/O CACHING EFFICIENCY 审中-公开
标题翻译：使用显式盘块缓存属性来增强I / O高速缓存效率
公开(公告)号：US20090070526A1
公开(公告)日：2009-03-12
申请号：US11854376
申请日：2007-09-12
申请人： R. Scott Tetrick , Dale J. Juenemann
发明人： R. Scott Tetrick , Dale J. Juenemann
IPC分类号： G06F12/08
CPC分类号： G06F12/0888 , G06F12/0866 , G06F2212/1021
摘要： A data caching method comprising identifying whether data stored in a first data block on a storage medium is cacheable; setting a first cacheability attribute associated with the first data block in a data structure to identify whether the data in the first data block is cacheable; monitoring I/O requests submitted for accessing target data in the first data block; determining whether the target data is cacheable based on the first cacheability attribute; and applying algorithms that implement cache policy to the target data, in response to determining that the target data is cacheable.
摘要翻译：一种数据缓存方法，包括：识别存储在存储介质上的第一数据块中的数据是否可高速缓存; 在数据结构中设置与第一数据块相关联的第一可缓存性属性，以识别第一数据块中的数据是否可高速缓存; 监视为第一数据块中访问目标数据而提交的I / O请求; 基于所述第一可缓存性属性来确定所述目标数据是否可缓存; 以及响应于确定所述目标数据是可缓存的，将实现高速缓存策略的算法应用于所述目标数据。

9. 发明授权

US5768585A System and method for synchronizing multiple processors during power-on self testing 失效
标题翻译：在开机自检期间同步多个处理器的系统和方法
公开(公告)号：US5768585A
公开(公告)日：1998-06-16
申请号：US561627
申请日：1995-11-21
申请人： R. Scott Tetrick , Raghu Murthi
发明人： R. Scott Tetrick , Raghu Murthi
IPC分类号： G06F9/06 , G06F9/445 , G06F11/22
CPC分类号： G06F9/4405 , G06F11/2284 , G06F15/177
摘要： A method for synchronizing testing of shared memory contained in a multi-processor computer system after reset. The method involves the steps of performing a wake-up procedure by a bootstrap processor on the other processors. Thus, the other processors can assist in testing the shared memory. Next, respective portions of the shared memory are allocated to each of the processors. Finally, upon completion of testing of its respective portion of the shared memory, each processor sets its unique storage unit synchronizing the processors at completion.
摘要翻译：一种用于在复位之后对包含在多处理器计算机系统中的共享存储器进行同步测试的方法。该方法包括以下步骤：在其他处理器上由自举处理器执行唤醒过程。因此，其他处理器可以帮助测试共享存储器。接下来，共享存储器的各个部分被分配给每个处理器。最后，在完成共享存储器的相应部分的测试之后，每个处理器设置其唯一存储单元在完成时使处理器同步。

10. 发明授权

US5737615A Microprocessor power control in a multiprocessor computer system 失效
标题翻译：多处理器计算机系统中的微处理器功率控制
公开(公告)号：US5737615A
公开(公告)日：1998-04-07
申请号：US421389
申请日：1995-04-12
申请人： R. Scott Tetrick
发明人： R. Scott Tetrick
IPC分类号： G06F1/32
CPC分类号： G06F1/3287 , G06F1/32 , Y02B60/1282 , Y02B60/32
摘要： A power down control mechanism for multiprocessor computer systems. A power down register is maintained for providing a power down control signal to the multiple processing units in the multiprocessing system. Individual processing units can be selectively onlined or offlined as needed. In addition, during system initialization, the power down mechanism of the present invention can be used for onlining additional processors and also used for preventing faulty processors from attempting to become the system's boot system processor.
摘要翻译：多处理器计算机系统的掉电控制机制。维持掉电寄存器以向多处理系统中的多个处理单元提供掉电控制信号。可以根据需要选择性地对线性处理单元进行单独处理。此外，在系统初始化期间，本发明的掉电机制可以用于对附加处理器进行加密，并且还用于防止故障处理器尝试成为系统的引导系统处理器。

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