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1. 发明授权

US08935458B2 Drive assisted system checkpointing via system restore points 有权
标题翻译：通过系统还原点驱动辅助系统检查点
公开(公告)号：US08935458B2
公开(公告)日：2015-01-13
申请号：US12984723
申请日：2011-01-05
申请人： Robert J. Royer, Jr. , Amber D. Huffman
发明人： Robert J. Royer, Jr. , Amber D. Huffman
IPC分类号： G06F12/00 , G06F11/14
CPC分类号： G06F11/1456 , G06F11/1451 , G06F11/1469
摘要： Systems and methods of managing computing system restore points may include an apparatus having logic to receive a command to start a restore point for a solid state drive (SSD). The logic may also conduct a context drop of an indirection table from a volatile memory of the SSD to a non-volatile memory of the SSD in response to the command to start the restore point.
摘要翻译：管理计算系统还原点的系统和方法可以包括具有接收用于启动固态驱动器（SSD）的还原点的命令的逻辑的装置。响应于启动还原点的命令，该逻辑还可以将间接表的上下文下降从SSD的易失性存储器进行到SSD的非易失性存储器。

2. 发明申请

US20140019676A1 REPURPOSING NAND READY/BUSY PIN AS COMPLETION INTERRUPT 审中-公开
标题翻译：将NAND READY / BUSY PIN作为完成中断
公开(公告)号：US20140019676A1
公开(公告)日：2014-01-16
申请号：US14024724
申请日：2013-09-12
申请人： Amber D. Huffman , Suryaprasad Kareenahalli , Robert J. Royer, JR. , Chai Huat Gan
发明人： Amber D. Huffman , Suryaprasad Kareenahalli , Robert J. Royer, JR. , Chai Huat Gan
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G11C16/10 , G11C16/32
摘要： A system and method of controlling a flash memory device such as a NAND memory device may involve receiving a command to execute an operation. A Ready/Busy contact of the memory device may be pulsed low in response to determining that execution of the operation has completed.
摘要翻译：控制诸如NAND存储设备的闪存设备的系统和方法可以包括接收执行操作的命令。响应于确定操作的执行已经完成，存储器件的就绪/忙触点可以被脉冲为低脉冲。

3. 发明申请

US20140003145A1 ARCHITECTURES AND TECHNIQUES FOR PROVIDING LOW-POWER STORAGE MECHANISMS 有权
标题翻译：提供低功耗存储机制的架构和技术
公开(公告)号：US20140003145A1
公开(公告)日：2014-01-02
申请号：US13537553
申请日：2012-06-29
申请人： JASON B. AKERS , Knut S. Grimsrud , Robert J. Royer, JR. , Richard P. Mangold , Sanjeev Trika
发明人： JASON B. AKERS , Knut S. Grimsrud , Robert J. Royer, JR. , Richard P. Mangold , Sanjeev Trika
IPC分类号： G11C14/00 , G11C7/00
CPC分类号： G06F3/0625 , G06F1/3287 , G06F3/0655 , G06F3/0688 , G06F11/1417 , G11C5/148 , G11C7/1072 , G11C14/0009 , Y02D10/171
摘要： Techniques to utilize a very low power state with a memory subsystem that includes one or more non-volatile memory devices and a volatile memory system. A memory controller is coupled with the one or more non-volatile memory devices and the volatile memory system. The memory controller comprising at least an embedded control agent and memory locations to store state information. The memory controller to selectively enable and disable the one or more non-volatile memory devices. The memory controller transfers the state information to the volatile memory system prior to entering a low power state. Control circuitry is coupled with the memory controller. The control circuitry to selectively enable and disable operation of the memory controller.
摘要翻译：利用包括一个或多个非易失性存储器件和易失性存储器系统的存储器子系统来利用非常低功率状态的技术。存储器控制器与一个或多个非易失性存储器件和易失性存储器系统耦合。存储器控制器至少包括嵌入式控制代理和存储状态信息的存储器位置。存储器控制器，用于选择性地启用和禁用一个或多个非易失性存储器件。存储器控制器在进入低功率状态之前将状态信息传送到易失性存储器系统。控制电路与存储器控制器耦合。所述控制电路用于选择性地启用和禁用所述存储器控制器的操作。

4. 发明授权

US08612666B2 Method and system for managing a NAND flash memory by paging segments of a logical to physical address map to a non-volatile memory 有权
标题翻译：用于通过将逻辑到物理地址映射的片段寻址到非易失性存储器来管理NAND闪存的方法和系统
公开(公告)号：US08612666B2
公开(公告)日：2013-12-17
申请号：US12495573
申请日：2009-06-30
申请人： Robert J. Royer, Jr. , Robert Faber , Brent Chartrand
发明人： Robert J. Royer, Jr. , Robert Faber , Brent Chartrand
IPC分类号： G06F12/00 , G06F12/10
CPC分类号： G06F12/0246 , G06F2212/7201 , G06F2212/7207
摘要： A method and system to facilitate paging of one or more segments of a logical-to-physical (LTP) address mapping structure, such as a table, to a non-volatile memory, such as a NAND flash memory. The LTP address mapping structure is part of an indirection system map associated with the non-volatile memory. By allowing one or more segments of the LTP address mapping structure to be paged to the non-volatile memory, the amount of volatile memory required to store the LTP address mapping structure is reduced while maintaining the benefits of the LTP address mapping structure. One or more segments of the logical to physical address mapping structure may be cached in volatile memory, and a size of each segment may be the same as or a multiple of a page size of the NAND flash memory. A lookup or segment table may be provided to indicate a location of each segment and may be optimized for sequential physical addresses.
摘要翻译：一种有助于将诸如表的逻辑到物理（LTP）地址映射结构的一个或多个段的寻呼的方法和系统提供给诸如NAND闪存之类的非易失性存储器。 LTP地址映射结构是与非易失性存储器相关联的间接系统映射的一部分。通过允许LTP地址映射结构的一个或多个段被分页到非易失性存储器，减少存储LTP地址映射结构所需的易失性存储器的量，同时保持LTP地址映射结构的优点。逻辑到物理地址映射结构的一个或多个段可以被缓存在易失性存储器中，并且每个段的大小可以与NAND闪速存储器的页面大小相同或倍数。可以提供查找或分段表以指示每个分段的位置并且可以针对顺序物理地址进行优化。

5. 发明授权

US08244970B2 Cache write integrity logging 有权
标题翻译：缓存写入完整性日志记录
公开(公告)号：US08244970B2
公开(公告)日：2012-08-14
申请号：US13074870
申请日：2011-03-29
申请人： Robert J. Royer, Jr. , Richard L. Coulson
发明人： Robert J. Royer, Jr. , Richard L. Coulson
IPC分类号： G06F12/00
CPC分类号： G06F12/0804 , G06F11/1417 , G06F11/1471 , G06F12/0802
摘要： An apparatus, as well as systems, methods, and articles can operate to record the address of write operations to a memory cached by a non-volatile cache prior to executing an operating system cache driver. In an embodiment, a non-volatile cache may be implemented by creating a device option read only memory (ROM), or modifying the associated computer basic input-output system (BIOS) to trap software interrupts associated with disk and other media access requests. Associated addresses, such as logical block addresses, can be stored in a log for data that is modified. The resulting log can be stored in a non-volatile medium, including the cache itself. If the available log space is not large enough to record all write activity prior to loading operating system drivers, a flag may be set to indicate the overrun condition.
摘要翻译：在执行操作系统高速缓存驱动器之前，设备以及系统，方法和文章可以操作以将写入操作的地址记录到由非易失性高速缓存的存储器中。在一个实施例中，可以通过创建设备选项只读存储器（ROM）或修改相关联的计算机基本输入 - 输出系统（BIOS）来捕获与磁盘和其他媒体访问请求相关联的软件中断来实现非易失性高速缓存。关联的地址，例如逻辑块地址，可以存储在修改的数据的日志中。所得到的日志可以存储在非易失性介质中，包括缓存本身。如果可用的日志空间不足以在加载操作系统驱动程序之前记录所有写入活动，则可以设置一个标志来指示超限状态。

6. 发明申请

US20120173794A1 DRIVE ASSISTED SYSTEM CHECKPOINTING 有权
标题翻译：驱动辅助系统检查
公开(公告)号：US20120173794A1
公开(公告)日：2012-07-05
申请号：US12984723
申请日：2011-01-05
申请人： Robert J. Royer, JR. , Amber D. Huffman
发明人： Robert J. Royer, JR. , Amber D. Huffman
IPC分类号： G06F12/00
CPC分类号： G06F11/1456 , G06F11/1451 , G06F11/1469
摘要： Systems and methods of managing computing system restore points may include an apparatus having logic to receive a command to start a restore point for a solid state drive (SSD). The logic may also conduct a context drop of an indirection table from a volatile memory of the SSD to a non-volatile memory of the SSD in response to the command to start the restore point.
摘要翻译：管理计算系统还原点的系统和方法可以包括具有接收用于启动固态驱动器（SSD）的还原点的命令的逻辑的装置。响应于启动还原点的命令，该逻辑还可以将间接表的上下文下降从SSD的易失性存储器进行到SSD的非易失性存储器。

7. 发明申请

US20110276827A1 DELTA CHECKPOINTS FOR A NON-VOLATILE MEMORY INDIRECTION TABLE 有权
标题翻译：用于非易失性存储器定义表的DELTA检查表
公开(公告)号：US20110276827A1
公开(公告)日：2011-11-10
申请号：US13084890
申请日：2011-04-12
申请人： Robert J. Royer, JR. , Richard Mangold
发明人： Robert J. Royer, JR. , Richard Mangold
IPC分类号： G06F12/00 , G06F11/07 , G06F12/02
CPC分类号： G06F11/1441 , G06F12/0246 , G06F2212/7207 , Y02D10/13
摘要： According to some embodiments, delta checkpoints are provided for a non-volatile memory indirection table to facilitate a recovery process after a power loss event.
摘要翻译：根据一些实施例，为非易失性存储器间接表提供增量检查点，以便于在功率损失事件之后恢复过程。

8. 发明申请

US20110153914A1 REPURPOSING NAND READY/BUSY PIN AS COMPLETION INTERRUPT 有权
标题翻译：将NAND READY / BUSY PIN作为完成中断
公开(公告)号：US20110153914A1
公开(公告)日：2011-06-23
申请号：US12643131
申请日：2009-12-21
申请人： Amber D. Huffman , Suryaprasad Kareenahalli , Robert J. Royer, JR. , Chai Huat Gan
发明人： Amber D. Huffman , Suryaprasad Kareenahalli , Robert J. Royer, JR. , Chai Huat Gan
IPC分类号： G06F12/00 , G06F12/02
CPC分类号： G06F12/0246 , G11C16/10 , G11C16/32
摘要： A system and method of controlling a flash memory device such as a NAND memory device may involve receiving a command to execute an operation. A Ready/Busy contact of the memory device may be pulsed low in response to determining that execution of the operation has completed.
摘要翻译：控制诸如NAND存储设备的闪存设备的系统和方法可以包括接收执行操作的命令。响应于确定操作的执行已经完成，存储器件的就绪/忙触点可以被脉冲为低脉冲。

9. 发明授权

US07328304B2 Interface for a block addressable mass storage system 有权
标题翻译：可寻址大容量存储系统的接口
公开(公告)号：US07328304B2
公开(公告)日：2008-02-05
申请号：US10788717
申请日：2004-02-27
申请人： Robert J. Royer, Jr. , Robert W. Faber , John I. Garney
发明人： Robert J. Royer, Jr. , Robert W. Faber , John I. Garney
IPC分类号： G06F12/00 , H03M13/00
CPC分类号： G06F12/0866 , B82Y10/00 , G06F3/0607 , G06F3/0659 , G06F3/0679 , G06F3/068 , G06F2212/222 , G06F2212/6028 , G11C11/22
摘要： A host controller interface to manage the complexity of accessing mass storage that takes into account the special handling needs of various memory technologies such as polymer memories.
摘要翻译：主机控制器接口，用于管理访问大容量存储的复杂性，其考虑到各种存储器技术（如聚合物存储器）的特殊处理需求。

10. 发明授权

US07152125B2 Dynamic master/slave configuration for multiple expansion modules 失效
公开(公告)号：US07152125B2
公开(公告)日：2006-12-19
申请号：US09963184
申请日：2001-09-25
申请人： John I. Garney , Robert J. Royer, Jr.
发明人： John I. Garney , Robert J. Royer, Jr.
IPC分类号： G06F13/00 , G06F13/24 , G06F3/00 , G06F15/76
CPC分类号： G06F9/5027 , G06F2209/5017
摘要： A computing system having expansion modules. One of the expansion modules is identified as a master module. The other modules act as slaves to the master module. The central processing unit routes a task to either the master module for portioning out or to all of the expansion modules. The master module then receives completion signals from all of the active slave modules and then provides only one interrupt to the central processing unit for that task.

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