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1. 发明申请

US20100332757A1 Integrated Pipeline Write Hazard Handling Using Memory Attributes 有权
标题翻译：集成管道使用内存属性写入危险程序
公开(公告)号：US20100332757A1
公开(公告)日：2010-12-30
申请号：US12495790
申请日：2009-06-30
申请人： Robert Nychka , Prashanth Karnamadakala , Nilesh Acharya
发明人： Robert Nychka , Prashanth Karnamadakala , Nilesh Acharya
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F9/3826 , G06F9/3834 , G06F9/3867
摘要： A system and method for write hazard handling are described, including a method comprising pre-computing a memory management unit policy for a write request using an address that is at least one clock cycle before data; registering the pre-computed memory management unit policy; using the pre-computed memory management unit policy to control a pipeline stall to ensure that non-bufferable writes are pipeline-protected, ensuring that no non-bufferable locations are bypassed from within the pipeline and all subsequent non-bufferable reads will get data from a final destination; bypassing a read request only after a corresponding write request is updated an write pending buffer; decoding the write request with the write request aligned to data; registering the write request in the write pending buffer; allowing arbitration logic to force the pipeline stall for a region that will have a write conflict; and stalling read requests to protect against write hazards.
摘要翻译：描述了用于写危险处理的系统和方法，包括一种方法，包括使用在数据之前至少一个时钟周期的地址来预先计算用于写入请求的存储器管理单元策略; 注册预先计算的存储器管理单元策略; 使用预先计算的存储器管理单元策略来控制流水线停顿以确保不可缓冲的写入被流水线保护，确保不在流水线内绕过不可缓冲的位置，并且所有后续的不可缓冲的读取将从最终目的地只有在相应的写入请求被更新为写入暂存缓冲器之后才绕过读取请求; 用与数据对准的写入请求对写入请求进行解码; 在写入待缓冲区中注册写入请求; 允许仲裁逻辑强制流水线停顿一个将有写冲突的区域; 并阻止读取请求以防止写入危险。

2. 发明申请

US20130046934A1 SYSTEM CACHING USING HETEROGENOUS MEMORIES 审中-公开
标题翻译：使用异构记忆的系统缓存
公开(公告)号：US20130046934A1
公开(公告)日：2013-02-21
申请号：US13209439
申请日：2011-08-15
申请人： Robert Nychka , William Michael Johnson , Steven D. Krueger
发明人： Robert Nychka , William Michael Johnson , Steven D. Krueger
IPC分类号： G06F12/08
CPC分类号： G06F12/0897
摘要： A caching circuit includes tag memories for storing tagged addresses of a first cache. On-chip data memories are arranged in the same die as the tag memories, and the on-chip data memories form a first sub-hierarchy of the first cache. Off-chip data memories are arranged in a different die as the tag memories, and the off-chip data memories form a second sub-hierarchy of the first cache. Sources (such as processors) are arranged to use the tag memories to service first cache requests using the first and second sub-hierarchies of the first cache.
摘要翻译：缓存电路包括用于存储第一高速缓存的标记地址的标签存储器。片上数据存储器被布置在与标签存储器相同的芯片中，并且片上数据存储器形成第一高速缓存的第一子层。片外数据存储器被布置在不同的管芯中作为标签存储器，并且片外数据存储器形成第一高速缓存的第二子层级。源（例如处理器）被布置为使用标签存储器来使用第一高速缓存的第一和第二子层次来服务第一高速缓存请求。

3. 发明授权

US08205057B2 Method and system for integrated pipeline write hazard handling using memory attributes 有权
标题翻译：使用记忆属性的集成管道写入危险处理的方法和系统
公开(公告)号：US08205057B2
公开(公告)日：2012-06-19
申请号：US12495790
申请日：2009-06-30
申请人： Robert Nychka , Prashanth Karnamadakala , Nilesh Acharya
发明人： Robert Nychka , Prashanth Karnamadakala , Nilesh Acharya
IPC分类号： G06F13/00 , G06F13/376 , G06F9/38
CPC分类号： G06F9/3826 , G06F9/3834 , G06F9/3867
摘要： In a system and method for write hazard handling a memory management unit policy is pre-computed for a write request using an address that is at least one clock cycle before data. The pre-computed memory management unit policy is registered and used for controlling a pipeline stall to ensure that a non-bufferable write is pipeline-protected, so that no non-bufferable location is bypassed from within the pipeline, and so that a subsequent non-bufferable read will get data from a final destination. A read request is bypassed only after a corresponding write request is updated in a write pending buffer. The write request is decoded with the write request aligned to data. The write request is registered in the write pending buffer. Arbitration logic is allowed to force the pipeline stall for a region that will have a write conflict. Read requests are stalled to protect against write hazards.
摘要翻译：在用于编写危险处理的系统和方法中，使用在数据之前至少一个时钟周期的地址，为写入请求预先计算存储器管理单元策略。预先计算的存储器管理单元策略被注册并用于控制流水线停顿以确保不可缓冲的写入被流水线保护，使得不在流水线内绕过不可缓冲的位置，缓存读取将从最终目的地获取数据。只有在写入挂起缓冲区中更新相应的写入请求之后，才能绕过读取请求。写入请求被解码，写入请求与数据对齐。写入请求被写入待写缓冲区。允许仲裁逻辑强制流水线停顿一个将有写冲突的区域。读取请求被阻止以防止写入危险。

4. 发明申请

US20090024796A1 High Performance Multilevel Cache Hierarchy 有权
标题翻译：高性能多级缓存层次结构
公开(公告)号：US20090024796A1
公开(公告)日：2009-01-22
申请号：US11779784
申请日：2007-07-18
申请人： Robert Nychka , Janardan Prasad , Nilesh Acharya , Aditya Rawal , Ambar Nawaz
发明人： Robert Nychka , Janardan Prasad , Nilesh Acharya , Aditya Rawal , Ambar Nawaz
IPC分类号： G06F13/00
CPC分类号： G06F12/0811
摘要： A digital system is provided with a hierarchical memory system having at least a first and second level cache and a higher level memory. If a requested data item misses in both the first cache level and in the second cache level, a line of data containing the requested data is obtained from a higher level of the hierarchical memory system. The line of data is allocated to both the first cache level and to the second cache level simultaneously.
摘要翻译：数字系统具有至少具有第一和第二级高速缓存和更高级存储器的分层存储器系统。如果请求的数据项在第一高速缓存级别和第二高速缓存级别都丢失，则从分层存储器系统的较高级别获得包含所请求数据的数据行。数据行同时分配给第一高速缓存级别和第二高速缓存级别。

5. 发明申请

US20100169578A1 CACHE TAG MEMORY 审中-公开
标题翻译：缓存标记内存
公开(公告)号：US20100169578A1
公开(公告)日：2010-07-01
申请号：US12347210
申请日：2008-12-31
申请人： Robert NYCHKA , William M. JOHNSON , Thang M. TRAN
发明人： Robert NYCHKA , William M. JOHNSON , Thang M. TRAN
IPC分类号： G06F12/08
CPC分类号： G06F12/084 , G06F2212/1016 , Y02D10/13
摘要： A system comprises tag memories and data memories. Sources use the tag memories with the data memories as a cache. Arbitration of a cache request is replayed, based on an arbitration miss and way hit, without accessing the tag memories. A method comprises receiving a cache request sent by a source out of a plurality of sources. The sources use tag memories with data memories as a cache. The method further comprises arbitrating the cache request, and replaying arbitration, based on an arbitration miss and way hit, without accessing the tag memories.
摘要翻译：一种系统包括标签存储器和数据存储器。来源使用数据存储器作为缓存的标签存储器。缓存请求的仲裁基于仲裁错误和方式命中而不访问标记存储器被重播。一种方法包括从多个源接收由源发送的高速缓存请求。来源使用具有数据存储器的标签存储器作为缓存。该方法还包括基于仲裁未决和方式命中来仲裁高速缓存请求和重播仲裁，而不访问标签存储器。

6. 发明授权

US07809889B2 High performance multilevel cache hierarchy 有权
标题翻译：高性能多级缓存层次结构
公开(公告)号：US07809889B2
公开(公告)日：2010-10-05
申请号：US11779784
申请日：2007-07-18
申请人： Robert Nychka , Janardan Prasad , Nilesh Acharya , Aditya Rawal , Ambar Nawaz
发明人： Robert Nychka , Janardan Prasad , Nilesh Acharya , Aditya Rawal , Ambar Nawaz
IPC分类号： G06F12/08
CPC分类号： G06F12/0811
摘要： A digital system is provided with a hierarchical memory system having at least a first and second level cache and a higher level memory. If a requested data item misses in both the first cache level and in the second cache level, a line of data containing the requested data is obtained from a higher level of the hierarchical memory system. The line of data is allocated to both the first cache level and to the second cache level simultaneously.
摘要翻译：数字系统具有至少具有第一和第二级高速缓存和更高级存储器的分层存储器系统。如果请求的数据项在第一高速缓存级别和第二高速缓存级别都丢失，则从分层存储器系统的较高级别获得包含所请求数据的数据行。数据行同时分配给第一高速缓存级别和第二高速缓存级别。

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