会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 2. 发明授权
    • Method and system for resetting fault tolerant computer system
    • 复位容错计算机系统的方法和系统
    • US08041995B2
    • 2011-10-18
    • US11304575
    • 2005-12-16
    • Shinji Abe
    • Shinji Abe
    • G06F11/00
    • G06F11/1679G06F11/1645G06F11/1658
    • There is disclosed a method capable of resetting a fault tolerant computer in complete synchronization among modules. The method includes a step of generating a reset requesting signal by one of the modules, a step of dividing the reset requesting signal to first and second reset requesting signals, a step of transmitting the second reset requesting signal to the other module, a step of delaying the first reset requesting signal in the one module by a time required for transmitting the second reset requesting signal to the other module, a step of resetting at least one CPU included in the one module by a first CPU reset signal generated based on the first reset requesting signal delayed in the one module, and a step of resetting at least one CPU included in the other module by a second CPU reset signal generated based on the second reset requesting signal transmitted to the other module.
    • 公开了能够在模块之间完全同步地重置容错计算机的方法。 该方法包括通过模块之一生成复位请求信号的步骤,将复位请求信号划分为第一和第二复位请求信号的步骤,向另一模块发送第二复位请求信号的步骤,步骤 将所述一个模块中的所述第一复位请求信号延迟传输所述另一个模块所需的时间;通过基于所述第一复位请求信号生成的第一CPU复位信号来复位所述一个模块中包括的至少一个CPU的步骤 在一个模块中延迟的复位请求信号,以及通过基于发送到另一个模块的第二复位请求信号而生成的第二CPU复位信号来复位包括在另一个模块中的至少一个CPU的步骤。
    • 9. 发明申请
    • METHOD FOR MANUFACTURING SEMICONDUCTOR OPTICAL DEVICE
    • 制造半导体光学器件的方法
    • US20080090315A1
    • 2008-04-17
    • US11868629
    • 2007-10-08
    • Shinji AbeKazushige Kawasaki
    • Shinji AbeKazushige Kawasaki
    • H01L21/00
    • H01S5/22B82Y20/00H01S5/0425H01S5/2009H01S5/2214H01S5/34333
    • After a metal cap layer is laminated on a semiconductor laminated structure, a waveguide ridge is formed, the waveguide ridge is coated with an SiO2 film, and a resist is applied; then, a resist pattern is formed, the resist pattern exposing the surface of the SiO2 film on the top of the waveguide ridge, and burying the SiO2 film in channels with a resist film having a surface higher than the surface of the metal cap layer of the waveguide ridge and lower than the surface of the SiO2 film of the waveguide ridge; the SiO2 film is removed by dry etching, using the resist pattern as a mask. The metal cap layer is removed by wet etching, and a p-GaN layer of the waveguide ridge is exposed to form the electrode layer.
    • 在半导体层叠结构上层压金属覆盖层之后,形成波导脊,将波导脊涂覆有SiO 2膜,并施加抗蚀剂; 然后,形成抗蚀剂图案,抗蚀剂图案将波导脊的顶部上的SiO 2膜的表面曝光,并且在SiO 2膜中埋入SiO 2膜, 具有比波导脊的金属盖层的表面高的表面的抗蚀剂膜,并且低于波导脊的SiO 2膜的表面; 通过干蚀刻除去SiO 2膜,使用抗蚀剂图案作为掩模。 通过湿蚀刻去除金属盖层,并且暴露波导脊的p-GaN层以形成电极层。