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1. 发明授权

US07991875B2 Link level retry scheme 有权
标题翻译：链路级重试方案
公开(公告)号：US07991875B2
公开(公告)日：2011-08-02
申请号：US11326982
申请日：2006-01-06
申请人： Ching-Tsun Chou , Suresh Chittor , Andalib Khan , Akhilesh Kumar , Phanindra K. Mannava , Rajee S. Ram , Sujoy Sen , Srinand Venkatesan , Kiran Padwekar
发明人： Ching-Tsun Chou , Suresh Chittor , Andalib Khan , Akhilesh Kumar , Phanindra K. Mannava , Rajee S. Ram , Sujoy Sen , Srinand Venkatesan , Kiran Padwekar
IPC分类号： G06F15/173 , G06F15/16 , G06F11/00 , G01R31/08 , H04L1/00 , H04L12/56 , H04L12/28 , H04L1/18 , H04J3/24
CPC分类号： H04L1/188 , H04L1/1614 , H04L1/1671 , H04L1/1874 , H04L29/06 , H04L69/324 , H04L2001/125
摘要： A link layer system is provided. The link layer system a first link layer control module and a retry queue for storing a transmitted data packet. The retry control module is coupled to the first link layer control module, which directs the retry queue to discard the transmitted data packet when an acknowledgment bit is received by the first link layer control module.
摘要翻译：提供了一个链路层系统。链路层系统是第一链路层控制模块和用于存储传输的数据分组的重试队列。重试控制模块耦合到第一链路层控制模块，当第一链路层控制模块接收到确认位时，引导重试队列丢弃所发送的数据分组。

2. 发明申请

US20070130353A1 Link level retry scheme 有权
标题翻译：链路级重试方案
公开(公告)号：US20070130353A1
公开(公告)日：2007-06-07
申请号：US11326982
申请日：2006-01-06
申请人： Ching-Tsun Chou , Suresh Chittor , Andalib Khan , Akhilesh Kumar , Phanindra Mannava , Rajee Ram , Sujoy Sen , Srinand Venkatesan , Kiran Padwekar
发明人： Ching-Tsun Chou , Suresh Chittor , Andalib Khan , Akhilesh Kumar , Phanindra Mannava , Rajee Ram , Sujoy Sen , Srinand Venkatesan , Kiran Padwekar
IPC分类号： G06F15/16
CPC分类号： H04L1/188 , H04L1/1614 , H04L1/1671 , H04L1/1874 , H04L29/06 , H04L69/324 , H04L2001/125
摘要： A link layer system is provided. The link layer system a first link layer control module and a retry queue for storing a transmitted data packet. The retry control module is coupled to the first link layer control module, which directs the retry queue to discard the transmitted data packet when an acknowledgment bit is received by the first link layer control module.
摘要翻译：提供了一个链路层系统。链路层系统是第一链路层控制模块和用于存储传输的数据分组的重试队列。重试控制模块耦合到第一链路层控制模块，当第一链路层控制模块接收到确认位时，引导重试队列丢弃所发送的数据分组。

3. 发明授权

US07016304B2 Link level retry scheme 失效
公开(公告)号：US07016304B2
公开(公告)日：2006-03-21
申请号：US09861260
申请日：2001-05-18
申请人： Ching-Tsun Chou , Suresh Chittor , Andalib Khan , Akhilesh Kumar , Phanindra K. Mannava , Rajee S. Ram , Sujoy Sen , Srinand Venkatesan , Kiran Padwekar
发明人： Ching-Tsun Chou , Suresh Chittor , Andalib Khan , Akhilesh Kumar , Phanindra K. Mannava , Rajee S. Ram , Sujoy Sen , Srinand Venkatesan , Kiran Padwekar
IPC分类号： G01R31/08
CPC分类号： H04L1/188 , H04L1/1614 , H04L1/1671 , H04L1/1874 , H04L29/06 , H04L69/324 , H04L2001/125
摘要： A link layer system is provided. The link layer system a first link layer control module and a retry queue for storing a transmitted data packet. The retry control module is coupled to the first link layer control module, which directs the retry queue to discard the transmitted data packet when an acknowledgment bit is received by the first link layer control module.

4. 发明授权

US6134622A Dual mode bus bridge for computer system 失效
标题翻译：计算机系统双模总线桥
公开(公告)号：US6134622A
公开(公告)日：2000-10-17
申请号：US13777
申请日：1998-01-26
申请人： Suvansh Kapur , Kevin Koschoreck , Srinand Venkatesan , D. Michael Bell
发明人： Suvansh Kapur , Kevin Koschoreck , Srinand Venkatesan , D. Michael Bell
IPC分类号： G06F9/38 , G06F13/40 , G06F13/38
CPC分类号： G06F9/3824 , G06F13/4045 , G06F13/4059 , G06F13/4081
摘要： A bus expander bridge is provided for interfacing first and second external buses (such as PCI buses) to a third bus. The bus expander bridge is configurable in either an independent mode in which the first and second external buses operate independently and a combined mode in which the first and second external buses are combined to create a single bus. The bus expander bridge includes a first set of data queues for routing data between the first external bus and the third bus, and a second set of data queues for routing data between the second external bus and the third bus. The bus expander bridge also includes a controller coupled to the first and second sets of data queues and operating the first and second sets of data queues in parallel for the independent mode. The controller routes even addressed data through the first set of data queues and routes odd addressed data through the second set of data queues for the combined mode.
摘要翻译：提供一个总线扩展器桥接器用于将第一和第二外部总线（例如PCI总线）与第三总线接口。总线扩展器桥可以以独立模式配置，其中第一和第二外部总线独立运行，以及组合模式，其中组合第一和第二外部总线以创建单个总线。总线扩展器桥包括用于在第一外部总线和第三总线之间路由数据的第一组数据队列，以及用于在第二外部总线和第三总线之间路由数据的第二组数据队列。总线扩展器桥还包括耦合到第一和第二组数据队列的控制器，并且为独立模式并行地操作第一和第二组数据队列。控制器通过第一组数据队列路由寻址数据，并通过组合模式的第二组数据队列路由奇数寻址数据。

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