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1. 发明申请

US20070070773A1 Static random access memory device having bit line voltage control for retain till accessed mode and method of operating the same 有权
标题翻译：具有用于保持直到访问模式的位线电压控制的静态随机存取存储器件及其操作方法
公开(公告)号：US20070070773A1
公开(公告)日：2007-03-29
申请号：US11237082
申请日：2005-09-28
申请人： Theodore Houston
发明人： Theodore Houston
IPC分类号： G11C5/14
CPC分类号： G11C11/413 , G11C7/12
摘要： A static random-access memory (SRAM) and a method of controlling bit line voltage. In one embodiment, the SRAM includes: (1) an array of SRAM cells organized in rows and columns, (2) bit lines associated with the columns, (3) a high voltage power supply configured to supply a high supply voltage, (4) a low voltage power supply configured to supply a low supply voltage, (5) bit line precharge circuitry configured to precharge at least one of the bit lines to a first voltage and (6) standby circuitry configured to maintain a voltage of the at least one bit line at at least a second voltage, the second voltage being lower than the first voltage and higher than the low supply voltage.
摘要翻译：静态随机存取存储器（SRAM）和一种控制位线电压的方法。在一个实施例中，SRAM包括：（1）以行和列组织的SRAM单元的阵列，（2）与列相关联的位线，（3）被配置为提供高电源电压的高电压电源（4 ）配置为提供低电源电压的低电压电源，（5）配置成将至少一个所述位线预充电到第一电压的位线预充电电路，以及（6）配置成保持所述至少一个电压的电压的备用电路在至少第二电压下的一个位线，所述第二电压低于所述第一电压并且高于所述低电源电压。

2. 发明申请

US20070035986A1 SRAM cell using separate read and write circuitry 有权
标题翻译： SRAM单元使用单独的读写电路
公开(公告)号：US20070035986A1
公开(公告)日：2007-02-15
申请号：US11202141
申请日：2005-08-11
申请人： Theodore Houston
发明人： Theodore Houston
IPC分类号： G11C11/00
CPC分类号： G11C11/413 , G11C7/1051 , G11C7/1069 , G11C7/1078 , G11C7/1096 , G11C11/412
摘要： The present invention provides circuitry for writing to and reading from an SRAM cell core, an SRAM cell, and an SRAM device. In one aspect, the circuitry includes a write circuit coupled to the SRAM cell core that includes at least one write transistor. The circuitry also includes a read circuit coupled to the SRAM cell core that includes at least one read transistor having a gate signal in common with the gate signal of the write transistor. The read transistor and the write transistor share a common gate signal, and each have an electrical characteristic, for which the electrical characteristic of the read transistor differs from that of the write transistor.
摘要翻译：本发明提供了用于向SRAM单元核，SRAM单元和SRAM器件进行写入和读取的电路。在一个方面，电路包括耦合到SRAM单元芯的写入电路，其包括至少一个写入晶体管。电路还包括耦合到SRAM单元芯的读取电路，其包括至少一个具有与写入晶体管的栅极信号共同的栅极信号的读取晶体管。读取晶体管和写入晶体管共享公共栅极信号，并且每个具有电特性，读取晶体管的电特性与写入晶体管的电特性不同。

3. 发明申请

US20070002617A1 Area efficient implementation of small blocks in an SRAM array 有权
标题翻译： SRAM阵列中小块的区域高效实现
公开(公告)号：US20070002617A1
公开(公告)日：2007-01-04
申请号：US11171033
申请日：2005-06-30
申请人： Theodore Houston , David Scott , Sudha Thiruvengadam
发明人： Theodore Houston , David Scott , Sudha Thiruvengadam
IPC分类号： G11C11/34
CPC分类号： G11C11/412 , H01L27/11 , H01L27/1104
摘要： An SRAM array and a dummy cell row structure is discussed that permits an SRAM array to be divided into segments isolated by a row pattern of dummy cells. The dummy cell structure avoids the use of special OPC conditions at the power supply line and block boundaries by providing a continuous cell array at the lower cell patterning levels in an area efficient implementation. In one implementation, the SRAM array comprises a first and second array block each comprising an SRAM cell having a first layout configuration, one or more of the dummy cells having a second layout configuration arranged along the row pattern associated with a wordline of the SRAM array, a first power supply voltage line connected to the first array block, and a second different power supply voltage line connected to the second array block. The first and second power supply voltage lines of the array blocks are further connected to the one or more dummy cells. Beneficially, the bitlines of the array may be continuous across the first and second array blocks and a dummy cell associated therewith.
摘要翻译：讨论了SRAM阵列和虚拟单元行结构，其允许将SRAM阵列划分成由虚拟单元的行图案隔离的段。虚拟单元结构避免了在电源线和块边界处使用特殊的OPC条件，通过在区域有效的实现中在较低单元图案化级别提供连续的单元阵列。在一个实现中，SRAM阵列包括第一和第二阵列块，每个阵列块包括具有第一布局配置的SRAM单元，一个或多个虚拟单元具有沿着与SRAM阵列的字线相关联的行图案布置的第二布局配置连接到第一阵列块的第一电源电压线和连接到第二阵列块的第二不同电源电压线。阵列块的第一和第二电源电压线还连接到一个或多个虚设单元。有利的是，阵列的位线可以在第一和第二阵列块和与其相关联的虚拟单元中是连续的。

4. 发明申请

US20050149887A1 Design method and system for optimum performance in integrated circuits that use power management 有权
标题翻译：使用电源管理的集成电路中的最佳性能设计方法和系统
公开(公告)号：US20050149887A1
公开(公告)日：2005-07-07
申请号：US10993815
申请日：2004-11-19
申请人： Amitava Chatterjee , David Scott , Theodore Houston , Song Zhao , Shaoping Tang , Zhiqiang Wu
发明人： Amitava Chatterjee , David Scott , Theodore Houston , Song Zhao , Shaoping Tang , Zhiqiang Wu
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： The present invention provides a method (100) of designing a circuit. The method comprises specifying (105) a design parameter for memory transistors and logic transistors and selecting (110) a test retention-mode bias voltage for the memory transistors. The method further comprises determining (115) a first relationship of a retention-mode leakage current and the design parameter at the test retention-mode bias voltage and obtaining (120) a second relationship of an active-mode drive current and the design parameter. The first and second relationships are used (125) to assess whether there is a range of values of the design parameter where the retention-mode leakage current and the active-mode drive current are within a predefined circuit specification. The method also includes adjusting (130) the test retention-mode bias voltage and repeating the determining and the using if the retention-mode total leakage current or the active-mode drive current is outside of the predefined circuit specification.
摘要翻译：本发明提供一种设计电路的方法（100）。该方法包括指定（105）存储晶体管和逻辑晶体管的设计参数，并选择（110）存储晶体管的测试保持模式偏置电压。所述方法还包括在所述测试保持模式偏置电压下确定（115）保持模式漏电流和所述设计参数的第一关系，并获得（120）所述有源模式驱动电流与所述设计参数的第二关系。使用第一和第二关系（125）来评估是否存在保持模式漏电流和有源模式驱动电流在预定电路规范内的设计参数值的范围。该方法还包括调整（130）测试保持模式偏置电压，并重复确定和使用如果保持模式总泄漏电流或有源模式驱动电流超出预定电路规范。

5. 发明申请

US20050128789A1 SRAM device and a method of operating the same to reduce leakage current during a sleep mode 有权
标题翻译： SRAM器件及其操作方法以在睡眠模式期间减少漏电流
公开(公告)号：US20050128789A1
公开(公告)日：2005-06-16
申请号：US10732970
申请日：2003-12-11
申请人： Theodore Houston
发明人： Theodore Houston
IPC分类号： G11C5/14 , G11C11/00 , G11C11/417 , G11C29/02
CPC分类号： G11C5/147 , G11C11/41 , G11C11/417 , G11C29/02 , G11C29/028 , G11C2029/0409 , G11C2029/5006
摘要： An SRAM device and a method of operating an SRAM device. In one embodiment, the SRAM device includes (1) an SRAM array coupled to row peripheral circuitry by a word line and coupled to column peripheral circuitry by bit lines and (2) a sleep mode voltage controller configured to provide both an array high supply voltage VADD that is lower than a high operating voltage VDD and an array low supply voltage VASS that is higher than a low operating voltage VSS to the SRAM array during a sleep mode.
摘要翻译：一种SRAM器件和一种操作SRAM器件的方法。在一个实施例中，SRAM器件包括（1）SRAM阵列，其通过字线耦合到行外围电路，并通过位线耦合到列外围电路;以及（2）睡眠模式电压控制器，其被配置为提供阵列高电源电压低于低工作电压V DD的高电压V DD和低阵列低电源电压V SUB ASS 在睡眠模式期间，向SRAM阵列提供SS 。

6. 发明申请

US20050036385A1 System for reducing row periphery power consumption in memory devices 有权
公开(公告)号：US20050036385A1
公开(公告)日：2005-02-17
申请号：US10945725
申请日：2004-09-21
申请人： Xiaowei Deng , Theodore Houston , Bryan Sheffield
发明人： Xiaowei Deng , Theodore Houston , Bryan Sheffield
IPC分类号： G11C8/08 , G11C11/417 , G11C11/34
CPC分类号： G11C8/08 , G11C11/417
摘要： The present invention provides a system for reducing row periphery power consumption in a semiconductor memory device, particularly during sleep mode operation. A memory device (100) according to the present invention has a row (106) of memory cells and driver circuitry (102) preceding the row of memory cells. The present invention provides an intervention circuit (114) instantiated within the driver circuitry proximal to the row of memory cells. The intervention circuit is operated to hold the row of memory cells at a desired state, while the driver circuitry (108, 110) preceding the intervention circuit is powered down.

7. 发明申请

US20050007831A1 Static random access memory device having decreased sensitivity to variations in channel physical characteristics 有权
标题翻译：静态随机存取存储器件对通道物理特性的变化具有降低的灵敏度
公开(公告)号：US20050007831A1
公开(公告)日：2005-01-13
申请号：US10616755
申请日：2003-07-10
申请人： Theodore Houston
发明人： Theodore Houston
IPC分类号： G11C11/412 , G11C5/00
CPC分类号： G11C11/412
摘要： A static random access memory (SRAM) device and a method of manufacturing the same. In one embodiment, the SRAM device includes: (1) a first bias voltage contact biasable to a first potential, (2) a second bias voltage contact biasable to a second potential that differs from the first potential and (3) a well having channels formed therein and connected to one of said first and second bias voltage contacts based on a transistor characteristic of said SRAM device that bears on static noise margin (SNM) and write trip voltage Vtrip.
摘要翻译：一种静态随机存取存储器（SRAM）装置及其制造方法。在一个实施例中，SRAM器件包括：（1）可偏置到第一电位的第一偏压接触器，（2）可偏置于不同于第一电位的第二电位的第二偏置电压接触器，以及（3）基于静态噪声容限（SNM）和写入跳闸电压Vtrip的所述SRAM器件的晶体管特性连接到所述第一和第二偏置电压触点之一。

8. 发明申请

US20050128852A1 HIGH PERFORMANCE SRAM DEVICE AND METHOD OF POWERING-DOWN THE SAME 有权
标题翻译：高性能SRAM器件及其相同功能的方法
公开(公告)号：US20050128852A1
公开(公告)日：2005-06-16
申请号：US10733485
申请日：2003-12-11
申请人： Xiaowei Deng , Hugh Mair , Theodore Houston , Luan Dang
发明人： Xiaowei Deng , Hugh Mair , Theodore Houston , Luan Dang
IPC分类号： G11C5/14 , G11C7/00 , G11C7/20 , G11C7/22 , G11C11/413 , G11C11/417
CPC分类号： G11C5/14 , G11C7/20 , G11C7/22 , G11C11/413 , G11C11/417 , G11C2207/2227
摘要： An SRAM device and a method of powering-down an SRAM device. In one embodiment, the SRAM device includes (1) an SRAM array coupled to an SRAM array low voltage source that provides a low SRAM array supply voltage VSB to the SRAM device and (2) main column peripheral circuitry having main pre-charge circuitry free of an SRAM header, coupled to the SRAM array by bit lines and coupled to a sleep mode controller through an associated main column peripheral driving circuitry that is configured to isolate the bit lines from a power supply during a sleep mode.
摘要翻译： SRAM器件和SRAM器件掉电的方法。在一个实施例中，SRAM器件包括（1）耦合到SRAM阵列低电压源的SRAM阵列，其向SRAM器件提供低SRAM阵列电源电压V SB，并且（2）主列周边具有不具有SRAM头的主预充电电路的电路，通过位线耦合到SRAM阵列，并通过相关联的主列外围驱动电路耦合到睡眠模式控制器，该主列外围驱动电路被配置为在睡眠模式。

9. 发明申请

US20080043542A1 STATIC RANDOM ACCESS MEMORY DEVICE HAVING REDUCED LEAKAGE CURRENT DURING ACTIVE MODE AND A METHOD OF OPERATING THEREOF 有权
标题翻译：在活动模式下具有减少的漏电流的静态随机存取存储器件及其操作方法
公开(公告)号：US20080043542A1
公开(公告)日：2008-02-21
申请号：US11875225
申请日：2007-10-19
申请人： Theodore HOUSTON
发明人： Theodore HOUSTON
IPC分类号： G11C7/22
CPC分类号： G11C11/417
摘要： An Static Random Access Memory (SRAM) device and a method of operating the same. In one embodiment, the SRAM device includes: (1) an SRAM array coupled to row peripheral circuitry by a word line and coupled to column peripheral circuitry by bit lines and (2) an array low voltage control circuitry that provides an enhanced low operating voltage VESS to the SRAM array during at least a portion of an active mode thereof.
摘要翻译：静态随机存取存储器（SRAM）装置及其操作方法。在一个实施例中，SRAM器件包括：（1）通过字线耦合到行外围电路并通过位线耦合到列外围电路的SRAM阵列;以及（2）阵列低电压控制电路，其提供增强的低工作电压在其活动模式的至少一部分期间向SRAM阵列提供V ESS。

10. 发明申请

US20080037346A1 MEMORY ARRAY WITH A DELAYED WORDLINE BOOST 有权
标题翻译：内存阵列与延迟的WORDLINE BOOST
公开(公告)号：US20080037346A1
公开(公告)日：2008-02-14
申请号：US11828476
申请日：2007-07-26
申请人： Theodore Houston
发明人： Theodore Houston
IPC分类号： G11C7/02
CPC分类号： G11C8/08 , G11C11/413
摘要： Methods and a circuit for writing to an SRAM memory cell of an array are discussed that provide improved static noise margin, and minimal risk of data upsets during write operations. The write method first rapidly raises the wordline to a lower read voltage level for access, then after a time delay that allows the cells in the selected row to establish a stabilizing differential voltage on the associated bitlines, raises the wordline voltage to a boosted or higher write voltage level. An SRAM bitline enhancement circuit may also be utilized in association with the SRAM memory array and writing method, for enhancing the differential voltage produced by an SRAM memory cell of the array on associated first and second bitlines of the array of conventional SRAM cells (e.g., a conventional 6T differential cell). In one implementation, the SRAM bitline enhancement circuit comprises a half-latch or a sense amplifier connected to associated bitline pairs of the array for amplifying the differential voltage.
摘要翻译：讨论了用于写入阵列的SRAM存储单元的方法和电路，其提供改进的静态噪声容限，并且在写入操作期间数据扰乱的风险最小。写入方法首先将字线迅速提高到更低的读取电压电平，然后在允许所选行中的单元在相关位线上建立稳定的差分电压的时间延迟之后，将字线电压提升到升压或更高写电压电平。也可以与SRAM存储器阵列和写入方法相关联地使用SRAM位线增强电路，用于增强由常规SRAM单元阵列的相关联的第一和第二位线上的阵列的SRAM存储器单元产生的差分电压（例如，常规6T差分电池）。在一个实现中，SRAM位线增强电路包括半锁存器或连接到用于放大差分电压的阵列的相关位线对的读出放大器。

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