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    • 5. 发明授权
    • Power conversion apparatus
    • 电力转换装置
    • US09257931B2
    • 2016-02-09
    • US13980285
    • 2012-01-18
    • Eiji TooyamaMorimitsu SekimotoToshiyuki Maeda
    • Eiji TooyamaMorimitsu SekimotoToshiyuki Maeda
    • H02P6/00H02J1/00H02P23/00H02M1/12H02P21/05
    • H02P23/0095H02M1/12H02P21/05H02P29/50
    • A power conversion apparatus is equipped with switching devices to perform power conversion of input AC power supplied from an AC power supply to output AC power having a predetermined voltage and a predetermined frequency, and to supply the power to a motor connected thereto. The apparatus includes a controller controlling switching of the switching devices, a capacitor smoothing a ripple generated by the switching of the switching devices, a current controller controlling a current flowing to the motor, and a voltage distortion corrector detecting a harmonic component caused by distortion in motor input power, and superimposing compensation values on an output of the current controller in accordance with a value of the harmonic component.
    • 电力转换装置配备有开关装置,对从交流电源供给的输入交流电力进行电力转换,输出具有预定电压和预定频率的交流电力,并向与其连接的电动机供电。 该装置包括控制切换装置的切换的控制器,平滑由切换装置的切换产生的纹波的电容器,控制流向马达的电流的电流控制器,以及检测由失真引起的谐波成分的电压失真校正器 马达输入功率,并根据谐波分量的值将补偿值叠加在电流控制器的输出上。
    • 6. 发明申请
    • POWER CONVERSION APPARATUS
    • 功率转换装置
    • US20130300334A1
    • 2013-11-14
    • US13980285
    • 2012-01-18
    • Eiji TooyamaMorimitsu SekimotoToshiyuki Maeda
    • Eiji TooyamaMorimitsu SekimotoToshiyuki Maeda
    • H02P23/00
    • H02P23/0095H02M1/12H02P21/05H02P29/50
    • A power conversion apparatus is equipped with switching devices to perform power conversion of input AC power supplied from an AC power supply to output AC power having a predetermined voltage and a predetermined frequency, and to supply the power to a motor connected thereto. The apparatus includes a controller controlling switching of the switching devices, a capacitor smoothing a ripple generated by the switching of the switching devices, a current controller controlling a current flowing to the motor, and a voltage distortion corrector detecting a harmonic component caused by distortion in motor input power, and superimposing compensation values on an output of the current controller in accordance with a value of the harmonic component.
    • 电力转换装置配备有开关装置,对从交流电源供给的输入交流电力进行电力转换,输出具有预定电压和预定频率的交流电力,并向与其连接的电动机供电。 该装置包括控制切换装置的切换的控制器,平滑由切换装置的切换产生的纹波的电容器,控制流向马达的电流的电流控制器,以及检测由失真引起的谐波成分的电压失真校正器 马达输入功率,并根据谐波分量的值将补偿值叠加在电流控制器的输出上。
    • 8. 发明授权
    • Plasma display device and method of driving the same
    • 等离子体显示装置及其驱动方法
    • US08199072B2
    • 2012-06-12
    • US12513687
    • 2007-12-07
    • Toshiyuki MaedaHidehiko Shoji
    • Toshiyuki MaedaHidehiko Shoji
    • G09G3/28
    • G09G3/2965G09G3/2927G09G2310/066
    • A scan electrode driving circuit applies a rising ramp waveform voltage to scan electrodes (SCN1 to SCNn) to generate a first setup discharge in a first period within a setup period, applies a dropping ramp waveform voltage to the scan electrodes (SCN1 to SCNn) to generate a second setup discharge in a second period following the first period within the setup period, and applies a first positive rectangular waveform voltage (Vs), a negative rectangular waveform voltage (Va), a second positive rectangular waveform voltage (Vs) and a dropping ramp waveform voltage to the scan electrodes (SCN1 to SCNn) in a third period following the second period within the setup period. A data electrode driving circuit applies a positive rectangular waveform voltage (Vd) to data electrodes (D1 to Dm) in a period after application of the first positive rectangular waveform voltage (Vs) to the scan electrodes (SCN1 to SCNn) and before application of the negative rectangular waveform voltage (Va) to the scan electrodes (SCN1 to SCNn) in the third period.
    • 扫描电极驱动电路向扫描电极(SCN1〜SCNn)施加上升斜坡波形电压,以在初始化期间内的第一期间产生第一次建立放电,向扫描电极(SCN1〜SCNn)施加下降斜坡波形电压至 在建立周期内的第一周期之后的第二周期中产生第二设定放电,并施加第一正矩形波形电压(Vs),负矩形波形电压(Va),第二正矩形波形电压(Vs)和 在设定期间内的第二期间之后的第三期间,向扫描电极(SCN1〜SCNn)施加斜坡波形电压。 数据电极驱动电路在对扫描电极(SCN1〜SCNn)施加第一正矩形波形电压(Vs)之后的期间内施加正的矩形波形电压(Vd)至数据电极(D1〜Dm) 在第三周期中对扫描电极(SCN1〜SCNn)的负矩形波形电压(Va)。
    • 9. 发明授权
    • Semiconductor integrated circuit and method of designing thereof based on TPI
    • 半导体集成电路及其基于TPI的设计方法
    • US08056036B2
    • 2011-11-08
    • US12153596
    • 2008-05-21
    • Toshiyuki MaedaToshiharu Asaka
    • Toshiyuki MaedaToshiharu Asaka
    • G06F9/455G06F17/50
    • G01R31/318583
    • A method of designing a semiconductor integrated circuit based on the TPI technique, comprising: (A) selecting a target node from a plurality of nodes included in a design circuit; (B) inserting a test point at the target node; (C) designating a delay time with respect to a test point path that is a path connected to the test point; and (D) laying out the design circuit such that a delay time of the test point path becomes the designated delay time. The (A) selecting includes: (A1) calculating delay times of fan-in paths and fan-out paths with respect to each of the plurality of nodes; and (A2) selecting the target node from the plurality of nodes based on the calculated delay times.
    • 一种基于TPI技术设计半导体集成电路的方法,包括:(A)从包括在设计电路中的多个节点中选择目标节点; (B)在目标节点插入一个测试点; (C)指定相对于连接到测试点的路径的测试点路径的延迟时间; 和(D)布置设计电路,使得测试点路径的延迟时间变为指定的延迟时间。 (A)选择包括:(A1)计算相对于所述多个节点中的每一个的扇入路径和扇出路径的延迟时间; 和(A2)基于所计算的延迟时间从多个节点中选择目标节点。
    • 10. 发明申请
    • SEMICONDUCTOR INTEGRATED CIRCUIT AND CORE TEST CIRCUIT
    • 半导体集成电路和核心测试电路
    • US20110175638A1
    • 2011-07-21
    • US13007366
    • 2011-01-14
    • Toshiyuki MAEDA
    • Toshiyuki MAEDA
    • G01R31/26
    • G01R31/318558G01R31/318563
    • A semiconductor circuit inhibiting the increase in the number of elements required to enable core circuit testing and a core test circuit enabling consecutive-pattern testing of a core circuit without increasing the number of terminals are provided. The semiconductor circuit includes a core circuit, a combinational circuit, a scan path for the combinational circuit with the scan path including cascaded scan flip-flops connected to input and output terminals of the combinational circuit, and scan path sharing circuits including multiplexers for allowing output signals of the core circuit to be inputted to the scan flip-flops, and allows a core circuit not included in the combinational circuit to be tested using the scan path for the combinational circuit. The core test circuit is provided with output shift registers for storing and outputting test results of plural test patterns outputted from output terminals of the core circuit to be eventually scanned out from the output shift registers.
    • 提供一种半导体电路,其抑制使核心电路测试所需要的元件数量的增加以及能够不增加端子数量而实现核心电路的连续图案测试的核心测试电路。 半导体电路包括核心电路,组合电路,组合电路的扫描路径,扫描路径包括连接到组合电路的输入和输出端子的级联扫描触发器,以及扫描路径共享电路,包括用于允许输出的多路复用器 要被输入到扫描触发器的核心电路的信号,并且允许不包括在组合电路中的核心电路使用用于组合电路的扫描路径进行测试。 核心测试电路设置有输出移位寄存器,用于存储并输出从输出移位寄存器最终扫描的核心电路的输出端输出的多个测试模式的测试结果。