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1. 发明申请

US20110193211A1 Surface Preparation of Die for Improved Bonding Strength 审中-公开
标题翻译：用于提高粘合强度的模具的表面处理
公开(公告)号：US20110193211A1
公开(公告)日：2011-08-11
申请号：US12701201
申请日：2010-02-05
申请人： Arvind Chandrasekaran , Shiqun Gu , Urmi Ray
发明人： Arvind Chandrasekaran , Shiqun Gu , Urmi Ray
IPC分类号： H01L23/538 , H01L21/56 , H01L21/60
CPC分类号： H01L23/3142 , H01L21/563 , H01L23/293 , H01L23/3128 , H01L23/3135 , H01L23/3192 , H01L24/13 , H01L24/16 , H01L25/0657 , H01L2224/0401 , H01L2224/05022 , H01L2224/05147 , H01L2224/0557 , H01L2224/05572 , H01L2224/05647 , H01L2224/05666 , H01L2224/13083 , H01L2224/131 , H01L2224/13147 , H01L2224/13155 , H01L2224/13166 , H01L2224/16145 , H01L2224/16225 , H01L2224/16227 , H01L2224/73203 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06568 , H01L2924/00014 , H01L2924/0002 , H01L2924/01029 , H01L2924/01033 , H01L2924/01057 , H01L2924/01078 , H01L2924/014 , H01L2924/14 , H01L2924/15311 , H01L2224/05552 , H01L2924/00
摘要： A surface preparation method for improved adhesion in an electronic package system. The method of improving adhesion in the electronic package system includes depositing a passivation layer on a bonding surface and roughening at least a portion of the passivation layer. A coating material is deposited on the passivation layer. The bonding surface can be part of a semiconductor or package substrate. The roughening process can be performed by a chemical or mechanical process. In another embodiment, an electronic package system includes a bonding surface of a semiconductor or package substrate. A passivation layer is deposited on the bonding surface and a portion of the passivation layer is roughened for improved adhesion. A coating material is deposited on the roughened portion of the passivation layer.
摘要翻译：一种用于改善电子封装系统中的附着力的表面处理方法。提高电子封装系统中的附着力的方法包括在接合表面上沉积钝化层并使钝化层的至少一部分变粗糙。在钝化层上沉积涂层材料。接合表面可以是半导体或封装衬底的一部分。粗化工艺可以通过化学或机械工艺进行。在另一个实施例中，电子封装系统包括半导体或封装衬底的接合表面。钝化层沉积在接合表面上，钝化层的一部分被粗糙化以提高粘附力。在钝化层的粗糙化部分上沉积涂层材料。

2. 发明申请

US20100155931A1 Embedded Through Silicon Stack 3-D Die In A Package Substrate 审中-公开
标题翻译：嵌入式硅片堆叠3-D封装在基板中
公开(公告)号：US20100155931A1
公开(公告)日：2010-06-24
申请号：US12340862
申请日：2008-12-22
申请人： Urmi Ray , Fifin Sweeney , Kenneth Kaskoun , Shiquin Gu , Thomas R. Toms
发明人： Urmi Ray , Fifin Sweeney , Kenneth Kaskoun , Shiquin Gu , Thomas R. Toms
IPC分类号： H01L23/538 , H01L21/50
CPC分类号： H01L25/0657 , H01L23/481 , H01L23/5383 , H01L23/5385 , H01L23/5389 , H01L25/03 , H01L2224/16225 , H01L2224/16227 , H01L2225/06513 , H01L2225/06541 , H01L2225/06568 , H01L2924/00014 , H01L2924/15311 , H01L2224/0401
摘要： An integrated circuit package has a die or die stack with through silicon vias embedded in a package substrate. A method of producing an integrated circuit package embeds at least one die with a through silicon via in a package substrate. The package substrate provides a protective cover for the die or die stack.
摘要翻译：集成电路封装具有通过硅通孔嵌入封装衬底中的管芯或管芯堆叠。一种制造集成电路封装件的方法在封装衬底中嵌入具有穿硅通孔的至少一个管芯。封装衬底提供用于管芯或管芯堆叠的保护盖。

3. 发明申请

US20110227230A1 THROUGH-SILICON VIA FABRICATION WITH ETCH STOP FILM 审中-公开
标题翻译：通过硅胶制成的薄膜
公开(公告)号：US20110227230A1
公开(公告)日：2011-09-22
申请号：US12727750
申请日：2010-03-19
申请人： Shiqun Gu , Yiming Li , Urmi Ray
发明人： Shiqun Gu , Yiming Li , Urmi Ray
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L21/76898
摘要： For a semiconductor wafer substrate having an inter layer dielectric, a through-silicon via may be formed in the substrate by first depositing an etch stop film on top of the inter layer dielectric, followed by etching an opening through the etch stop film, the interlayer dielectric, and into the substrate. A dielectric liner is then deposited over the etch stop film and into the opening. For some embodiments, the dielectric liner may be etched away except for those portions adhering to the sidewall of the opening. Then a conductive material may be deposited into the opening and on the etch stop film. The excess conductive material may then be removed, and for some embodiments the etch stop film may also be removed.
摘要翻译：对于具有层间电介质的半导体晶片衬底，可以在衬底中形成通硅通孔，首先在层间电介质的顶部上沉积蚀刻停止膜，然后蚀刻通过蚀刻停止膜，中间层电介质，并进入衬底。然后将电介质衬垫沉积在蚀刻停止膜上并进入开口中。对于一些实施例，除了粘附到开口的侧壁上的那些部分之外，电介质衬垫可被蚀刻掉。然后可以将导电材料沉积到开口中和蚀刻停止膜上。然后可以除去过量的导电材料，并且对于一些实施例，也可以去除蚀刻停止膜。

4. 发明申请

US20110012239A1 Barrier Layer On Polymer Passivation For Integrated Circuit Packaging 审中-公开
标题翻译：聚合物钝化阻挡层用于集成电路封装
公开(公告)号：US20110012239A1
公开(公告)日：2011-01-20
申请号：US12758311
申请日：2010-04-12
申请人： Shiqun Gu , Urmi Ray , Yiming Li , Arvind Chandrasekaran
发明人： Shiqun Gu , Urmi Ray , Yiming Li , Arvind Chandrasekaran
IPC分类号： H01L29/06 , H01L21/768 , H01L21/311
CPC分类号： H01L23/3192 , H01L21/6836 , H01L23/3142 , H01L24/11 , H01L24/13 , H01L24/94 , H01L2221/6834 , H01L2224/10126 , H01L2224/1147 , H01L2224/1191 , H01L2224/13022 , H01L2224/13099 , H01L2224/16225 , H01L2224/94 , H01L2924/0001 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01033 , H01L2924/14 , H01L2924/1433 , H01L2224/11 , H01L2224/03
摘要： A barrier layer deposited on the passivation layer of a semiconductor die decreases adhesion of glue used during stacking of semiconductor dies by altering chemical or structural properties of the passivation layer. During detachment of a carrier wafer from a wafer, the barrier layer reduces glue residue on the wafer by modifying the surface of the passivation layer. The barrier layer may be insulating films such as silicon dioxide, silicon nitride, silicon carbide, polytetrafluoroethylene, organic layers, or epoxy and may be less than two micrometers in thickness. Additionally, the barrier layer may be used to reduce topography of the semiconductor die to decrease adhesion of glues.
摘要翻译：沉积在半导体管芯的钝化层上的阻挡层通过改变钝化层的化学或结构特性来降低在半导体管芯堆叠期间使用的胶粘附力。在从晶片分离载体晶片时，阻挡层通过改变钝化层的表面来减少晶片上的胶残余物。阻挡层可以是诸如二氧化硅，氮化硅，碳化硅，聚四氟乙烯，有机层或环氧树脂之类的绝缘膜，并且其厚度可以小于2微米。此外，阻挡层可以用于减少半导体管芯的形貌以降低胶粘剂的粘附。

5. 发明申请

US20100314725A1 Stress Balance Layer on Semiconductor Wafer Backside 审中-公开
标题翻译：半导体晶片背面的应力平衡层
公开(公告)号：US20100314725A1
公开(公告)日：2010-12-16
申请号：US12483759
申请日：2009-06-12
申请人： Shiqun Gu , Arvind Chandrasekaran , Urmi Ray , Yiming Li
发明人： Shiqun Gu , Arvind Chandrasekaran , Urmi Ray , Yiming Li
IPC分类号： H01L23/00 , H01L21/306 , H01L21/31
CPC分类号： H01L25/0657 , H01L21/76898 , H01L23/562 , H01L2224/16 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2924/00011 , H01L2924/00014 , H01L2224/0401
摘要： A semiconductor component (such as a semiconductor wafer or semiconductor die) includes a substrate having a front side and a back side. The semiconductor die/wafer also includes a stress balance layer on the back side of the substrate. An active layer deposited on the front side of the substrate creates an unbalanced stress in the semiconductor wafer/die. The stress balance layer balances stress in the semiconductor wafer/die. The stress in the stress balance layer approximately equals the stress in the active layer. Balancing stress in the semiconductor component prevents warpage of the semiconductor wafer/die.
摘要翻译：半导体元件（例如半导体晶片或半导体晶片）包括具有正面和背面的基板。半导体管芯/晶片还包括在衬底背面的应力平衡层。沉积在基板的正面上的有源层在半导体晶片/管芯中产生不平衡的应力。应力平衡层平衡半导体晶片/模具中的应力。应力平衡层中的应力大致等于有源层中的应力。在半导体部件中平衡应力可以防止半导体晶片/裸片翘曲。

6. 发明申请

US20110147895A1 Apparatus and Method for Controlling Semiconductor Die Warpage 有权
标题翻译：用于控制半导体模具翘曲的装置和方法
公开(公告)号：US20110147895A1
公开(公告)日：2011-06-23
申请号：US12640111
申请日：2009-12-17
申请人： Xue Bai , Urmi Ray
发明人： Xue Bai , Urmi Ray
IPC分类号： H01L23/00 , H01L21/768 , G06F17/50
CPC分类号： H01L23/562 , H01L23/3128 , H01L23/3677 , H01L23/481 , H01L2224/16225 , H01L2924/15311
摘要： A semiconductor die has through silicon vias arranged to reduce warpage. The through silicon vias adjust the coefficient of thermal expansion of the semiconductor die, permit substrate deformation, and also relieve residual stress. The through silicon vias may be located in the edges and/or corners of the semiconductor die. The through silicon vias are stress relief vias that can be supplemented with round corner vias to reducing warpage of the semiconductor die.
摘要翻译：半导体管芯通过布置成减小翘曲的硅通孔。通过硅通孔调节半导体管芯的热膨胀系数，允许基板变形，并且还可以减轻残余应力。贯通硅通孔可以位于半导体管芯的边缘和/或拐角处。通孔硅通孔是可以补充有圆形拐角通孔的减压通孔，以减少半导体管芯的翘曲。

7. 发明授权

US06260386B1 Optical fiber preform cleaning method 失效
标题翻译：光纤预制棒清洗方法
公开(公告)号：US06260386B1
公开(公告)日：2001-07-17
申请号：US08208557
申请日：1994-03-10
申请人： Jeffrey Jonathan Evans , Siu-Ping Hong , Urmi Ray , Trudy Murrell Thiele
发明人： Jeffrey Jonathan Evans , Siu-Ping Hong , Urmi Ray , Trudy Murrell Thiele
IPC分类号： C03B3700
CPC分类号： C03B37/012 , B08B7/0021
摘要： Glass preforms are cleaned by contacting each preform (11) with supercritical carbon dioxide which dissolves residual index-matching oil on the preform. The liquefied carbon dioxide is then converted to gaseous carbon dioxide which conveniently separates the index-matching oil so that it can be recovered and reused. The gaseous carbon dioxide is likewise recycled for use in cleaning other preforms, and so there is substantially no waste.
摘要翻译：通过使每个预制件（11）与超临界二氧化碳接触来清洁玻璃预成型件，所述超临界二氧化碳在预成型件上溶解剩余的折射率匹配油。然后将液化的二氧化碳转化为气态二氧化碳，其方便地分离指数匹配油，使其可以回收和再利用。气态二氧化碳同样被循环用于清洁其它预型件，因此基本上没有浪费。

8. 发明授权

US08710629B2 Apparatus and method for controlling semiconductor die warpage 有权
标题翻译：用于控制半导体模具翘曲的装置和方法
公开(公告)号：US08710629B2
公开(公告)日：2014-04-29
申请号：US12640111
申请日：2009-12-17
申请人： Xue Bai , Urmi Ray
发明人： Xue Bai , Urmi Ray
IPC分类号： H01L23/00 , H01L21/768 , G06F17/50
CPC分类号： H01L23/562 , H01L23/3128 , H01L23/3677 , H01L23/481 , H01L2224/16225 , H01L2924/15311
摘要： A semiconductor die has through silicon vias arranged to reduce warpage. The through silicon vias adjust the coefficient of thermal expansion of the semiconductor die, permit substrate deformation, and also relieve residual stress. The through silicon vias may be located in the edges and/or corners of the semiconductor die. The through silicon vias are stress relief vias that can be supplemented with round corner vias to reducing warpage of the semiconductor die.
摘要翻译：半导体管芯通过布置成减小翘曲的硅通孔。通过硅通孔调节半导体管芯的热膨胀系数，允许基板变形，并且还可以减轻残余应力。贯通硅通孔可以位于半导体管芯的边缘和/或拐角处。通孔硅通孔是可以补充有圆形拐角通孔的减压通孔，以减少半导体管芯的翘曲。

9. 发明申请

US20110193212A1 Systems and Methods Providing Arrangements of Vias 审中-公开
标题翻译：系统和方法提供安排通风口
公开(公告)号：US20110193212A1
公开(公告)日：2011-08-11
申请号：US12701642
申请日：2010-02-08
申请人： Shiqun Gu , Matthew Michael Nowak , Durodami J. Lisk , Thomas R. Toms , Urmi Ray , Jungwon Suh , Arvind Chandrasekaran
发明人： Shiqun Gu , Matthew Michael Nowak , Durodami J. Lisk , Thomas R. Toms , Urmi Ray , Jungwon Suh , Arvind Chandrasekaran
IPC分类号： H01L23/522 , H01L21/768
CPC分类号： H01L23/5286 , H01L23/3677 , H01L23/481 , H01L24/05 , H01L24/13 , H01L24/14 , H01L24/48 , H01L24/81 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2224/05093 , H01L2224/13009 , H01L2224/13025 , H01L2224/13028 , H01L2224/131 , H01L2224/14505 , H01L2224/16145 , H01L2224/16146 , H01L2224/17517 , H01L2224/48091 , H01L2224/48227 , H01L2224/81136 , H01L2224/81193 , H01L2224/81801 , H01L2225/06513 , H01L2225/06541 , H01L2225/06562 , H01L2924/00014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/014 , H01L2924/14 , H01L2924/1433 , H01L2924/15311 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor chip includes an array of electrical contacts and multiple vias coupling at least one circuit in the semiconductor chip to the array of electrical contacts. A first one of the electrical contacts of the array of electrical contacts is coupled to N vias, and a second one of the electrical contacts of the array of electrical contacts is coupled to M vias. M and N are positive integers of different values.
摘要翻译：半导体芯片包括电连接阵列和将半导体芯片中的至少一个电路耦合到电接触阵列的多个通孔。电触点阵列的电触点中的第一个耦合到N个通孔，并且电触点阵列的电触点中的第二个耦合到M个通孔。 M和N是不同值的正整数。

10. 发明授权

US5501761A Method for stripping conformal coatings from circuit boards 失效
标题翻译：从电路板剥离保形涂层的方法
公开(公告)号：US5501761A
公开(公告)日：1996-03-26
申请号：US324550
申请日：1994-10-18
申请人： Jeffrey J. Evans , Leslie A. Guth , Urmi Ray
发明人： Jeffrey J. Evans , Leslie A. Guth , Urmi Ray
IPC分类号： B29C63/00 , H05K3/28 , B32B35/00
CPC分类号： B29C63/0013 , H05K3/284 , B29C2793/00 , B29L2031/3425 , Y10S156/922 , Y10T156/11 , Y10T156/19 , Y10T29/49726 , Y10T29/49821
摘要： In preparation for removing a protective adherent covercoat from a circuit board that is to be repaired, the surface integrity of the coating is altered (for example, by making incisions therein). Subsequently, the coated circuit board is subjected to supercritical carbon dioxide in a processing chamber. Following this process, the coating is easily lifted from the board.
摘要翻译：为了从要修复的电路板上除去保护性粘合性覆盖层，改变涂层的表面完整性（例如通过在其中进行切口）。随后，涂覆的电路板在处理室中经受超临界二氧化碳。在该过程之后，涂层容易从板上提起。

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