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1. 发明授权

US08410602B2 Cooling system for semiconductor devices 有权
公开(公告)号：US08410602B2
公开(公告)日：2013-04-02
申请号：US11974595
申请日：2007-10-15
申请人： Venkat Natarajan , Arun Chandrasekhar , Pr Patel , Vittal Kini
发明人： Venkat Natarajan , Arun Chandrasekhar , Pr Patel , Vittal Kini
IPC分类号： H01L23/34 , H01L23/10
CPC分类号： H01L23/367 , H01L2924/0002 , H01L2924/00
摘要： In one embodiment, the present invention includes a socket for a semiconductor package, where the socket has a frame with a segmented design, where socket streets are located between the segments. One or more of the streets may include a conduit to enable thermal transfer during operation of the semiconductor package. Other embodiments are described and claimed.

2. 发明申请

US20060053325A1 Storing system information in a low-latency persistent memory device upon transition to a lower-power state 审中-公开
标题翻译：将系统信息存储在低延迟持久存储器件中，以转换到较低功耗状态
公开(公告)号：US20060053325A1
公开(公告)日：2006-03-09
申请号：US10934655
申请日：2004-09-03
申请人： Ram Chary , Vittal Kini , Rick Leiss , Pradeep Sebestian
发明人： Ram Chary , Vittal Kini , Rick Leiss , Pradeep Sebestian
IPC分类号： G06F1/26
CPC分类号： G06F11/323
摘要： According to some embodiments, it may be determined that a processing system is to transition from a higher-power state to a lower-power state. System information may then be copied from a volatile memory device to a low-latency persistent memory device, and it may be arranged for the processing system to transition from the higher-power state to the lower-power state.
摘要翻译：根据一些实施例，可以确定处理系统将从较高功率状态转换到较低功率状态。然后，系统信息可以从易失性存储器件复制到低等待时间持久存储器件，并且其可以被布置为使处理系统从较高功率状态转换到较低功率状态。

3. 发明授权

US07471648B2 Integrating video, voice and data traffic in a single conferencing system 有权
标题翻译：将视频，语音和数据流量整合到一个会议系统中
公开(公告)号：US07471648B2
公开(公告)日：2008-12-30
申请号：US10859878
申请日：2004-06-02
申请人： David B. Andersen , David B. Johnson , Vittal Kini
发明人： David B. Andersen , David B. Johnson , Vittal Kini
IPC分类号： H04L12/16 , H04J1/00
CPC分类号： H04J1/05
摘要： Video, voice and data are integrated using existing telephone connections by using a video network server to receive and transmit video signals to and from clients using telephone wires. Client frequency division multiplexing couplers, each associated with one of the clients, receive video and telephone signals from the client and frequency multiplex them onto the telephone wires for transmission. They also receive video signals from the server and frequency demultiplex them for transmission to the client. A video frequency division multiplexing coupler connected between the video network server and each of the client frequency division multiplexing couplers receive the video and telephone signals from the clients and transmit only the video signals to the video network server. A telephone frequency division multiplexing coupler connected between a telephone network switch and each of the client frequency division multiplexing couplers receive the video and telephone signals from the clients and transmit only the telephone signals to the telephone network switch.
摘要翻译：视频，语音和数据通过使用视频网络服务器使用现有的电话连接进行集成，以使用电话线接收和传送视频信号到客户端。每个客户端频分复用耦合器与客户端之一相连，从客户接收视频和电话信号，并将其频率复用到电话线上进行传输。它们还接收来自服务器的视频信号，并对其进行频率解复用以传输到客户端。连接在视频网络服务器和每个客户端频分复用耦合器之间的视频分频复用耦合器从客户端接收视频和电话信号，并将视频信号仅传送到视频网络服务器。连接在电话网络交换机和每个客户端频分复用耦合器之间的电话频分复用耦合器从客户端接收视频和电话信号，并将电话信号仅传送到电话网络交换机。

4. 发明授权

US06894987B1 Method and apparatus for integrating video, voice and computer data traffic in a single, conferencing system using existing telephone and CATV connections 失效
标题翻译：将视频，语音和计算机数据流量集成在使用现有电话和CATV连接的单个会议系统中的方法和装置
公开(公告)号：US06894987B1
公开(公告)日：2005-05-17
申请号：US09619522
申请日：2000-07-19
申请人： David B. Andersen , David B. Johnson , Vittal Kini
发明人： David B. Andersen , David B. Johnson , Vittal Kini
IPC分类号： H04J1/05 , H04L12/16 , H04J1/00
CPC分类号： H04J1/05
摘要： Video, voice and data are integrated using existing telephone connections by using a video network server to receive and transmit video signals to and from clients using telephone wires. Client frequency division multiplexing couplers, each associated with one of the clients, receive video and telephone signals from the client and frequency multiplex them onto the telephone wires for transmission. They also receive video signals from the server and frequency demultiplex them for transmission to the client. A video frequency division multiplexing coupler connected between the video network server and each of the client frequency division multiplexing couplers receive the video and telephone signals from the clients and transmit only the video signals to the video network server. A telephone frequency division multiplexing coupler connected between a telephone network switch and each of the client frequency division multiplexing couplers receive the video and telephone signals from the clients and transmit only the telephone signals to the telephone network switch.
摘要翻译：视频，语音和数据通过使用视频网络服务器使用现有的电话连接进行集成，以使用电话线接收和传送视频信号到客户端。每个客户端频分复用耦合器与客户端之一相连，从客户接收视频和电话信号，并将其频率复用到电话线上进行传输。它们还接收来自服务器的视频信号，并对其进行频率解复用以传输到客户端。连接在视频网络服务器和每个客户端频分复用耦合器之间的视频分频复用耦合器从客户端接收视频和电话信号，并将视频信号仅传送到视频网络服务器。连接在电话网络交换机和每个客户端频分复用耦合器之间的电话频分复用耦合器从客户端接收视频和电话信号，并将电话信号仅传送到电话网络交换机。

5. 发明授权

US4821271A Methods and circuits for checking integrated circuit chips having programmable outputs 失效
标题翻译：用于检查具有可编程输出的集成电路芯片的方法和电路
公开(公告)号：US4821271A
公开(公告)日：1989-04-11
申请号：US79444
申请日：1987-07-30
申请人： M. Vittal Kini , Mark S. Myers , Sunil Shenoy
发明人： M. Vittal Kini , Mark S. Myers , Sunil Shenoy
IPC分类号： G01R31/28 , G06F11/16 , G06F11/22 , G06F11/267 , H01L21/66
CPC分类号： G06F11/1608 , G06F11/2273 , G06F11/267
摘要： A functional-redundancy checking logic for checking identical chips whose outputs are time-variant programmable. Window logic (40, 60) on each chip creates a window associated with each programmed transition, set pulse (14) and reset pulse (15). For the set pulse (14), on the rising edge (42) of the window, an error flip-flop (50) is set. The flip-flop is merely set at this time; an error is not flagged. The window remains open for a fixed time period. During the time period that the window is open, if the output pin (24) is ever correctly asserted, then the flip-flop (50) is reset, thus clearing the error flag. However, if the pin (24) always remains incorrectly asserted, indicating an error, then the error flip-flop (50) remains set. When the window closes on the falling edge (46) of the window pulse, an error report pulse is created via the AND (52). The value on the flip-flop (50) at this time is reported as an error (54). An identical circuit checks the programmable reset pulse ( 15).
摘要翻译：用于检查输出为时变可编程的相同芯片的功能冗余校验逻辑。每个芯片上的窗口逻辑（40,60）创建与每个编程的转换，设置脉冲（14）和复位脉冲（15）相关联的窗口。对于设定脉冲（14），在窗口的上升沿（42），设置错误触发器（50）。触发器只是在这个时候设置的; 没有标记错误。窗口保持打开一段固定的时间段。在窗口打开的时间段期间，如果输出引脚（24）被正确地置位，则触发器（50）被复位，从而清除错误标志。但是，如果引脚（24）始终保持不正确的状态，指示错误，则错误触发器（50）保持置1。当窗口脉冲的下降沿（46）关闭时，通过AND（52）创建错误报告脉冲。此时触发器（50）上的值被报告为错误（54）。相同的电路检查可编程复位脉冲（15）。

6. 发明申请

US20090096086A1 Cooling system for semiconductor devices 有权
标题翻译：半导体器件冷却系统
公开(公告)号：US20090096086A1
公开(公告)日：2009-04-16
申请号：US11974595
申请日：2007-10-15
申请人： Venkat Natarajan , Arun Chandrasekhar , Pr Patel , Vittal Kini
发明人： Venkat Natarajan , Arun Chandrasekhar , Pr Patel , Vittal Kini
IPC分类号： H01L23/34
CPC分类号： H01L23/367 , H01L2924/0002 , H01L2924/00
摘要： In one embodiment, the present invention includes a socket for a semiconductor package, where the socket has a frame with a segmented design, where socket streets are located between the segments. One or more of the streets may include a conduit to enable thermal transfer during operation of the semiconductor package. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括用于半导体封装的插座，其中插座具有分段设计的框架，其中插座街道位于片段之间。一个或多个街道可以包括导管，以在半导体封装的操作期间实现热传递。描述和要求保护其他实施例。

7. 发明授权

US4785428A Programmable memory array control signals 失效
标题翻译：可编程存储器阵列控制信号
公开(公告)号：US4785428A
公开(公告)日：1988-11-15
申请号：US63468
申请日：1987-06-18
申请人： Atiq Bajwa , Robert Duzett , M. Vittal Kini , Kent Mason , Mark S. Myers , Sunil Shenoy
发明人： Atiq Bajwa , Robert Duzett , M. Vittal Kini , Kent Mason , Mark S. Myers , Sunil Shenoy
IPC分类号： G11C11/407 , G11C7/22 , G11C11/401 , G11C13/00
CPC分类号： G11C7/22
摘要： The waveform of a strobe type signal (70) is specified by two bit strings (72, 74) stored in the RAM (20), one bit string (72) denoting when the strobe is to be reset and the other (74) denoting when the strobe is to be set. The bit positions in the bit strings correspond with clock cycles (76) taken for a DRAM memory access. The bit positions are written by means of addressable registers (71) corresponding to rows (e.g. 80-87) of the RAM. A one bit in the set bit string (72) causes the signal (70) to be asserted in the corresponding clock cycle of the request. A one bit in the reset bit string causes the signal (70) to be de-asserted in the corresponding clock cycle of the request. The set and reset times are fine-tuned to a fraction of a cycle by providing a multi-bit fractional cycle index field (78) to accompany each bit string. If a two bit quarter cycle index (QCI) field is used, the boundaries of the quarter cycles are numbered from 0 to 3. 0 coincides with the first quarter cycle after the leading edge of a clock cycle and 3 coincides with the clock cycle boundary. The one bit in the set or reset bit string denotes the cycle in which a transition is to take place, while the quarter cycle index field encoding denotes the precise quarter of the cycle in which the transition takes place.
摘要翻译：选通型信号（70）的波形由存储在RAM（20）中的两个位串（72,74）指定，一个位串（72）表示当选通复位时，另一个（74）表示当频闪被设置时。位串中的位位置对应于用于DRAM存储器访问的时钟周期（76）。位位置通过对应于RAM的行（例如80-87）的可寻址寄存器（71）来写入。设置位串（72）中的一位使得信号（70）在请求的相应时钟周期中被断言。复位位串中的一位使得信号（70）在请求的相应时钟周期中被解除断言。通过提供一个多比特分数循环索引字段（78）来配合每个位串，将设置和复位时间微调到一个周期的一小部分。如果使用两比特四分之一周期指数（QCI）字段，则四分之一周期的边界从0到3编号，与时钟周期前沿之后的第一个四分之一周期相符，3与时钟周期边界一致。置位或复位位串中的一位表示要进行转换的周期，而四分之一周期指数字段编码表示发生转换的周期的精确四分之一。

8. 发明授权

US07729121B1 Removable package underside device attach 有权
标题翻译：可拆卸包装下装置附件
公开(公告)号：US07729121B1
公开(公告)日：2010-06-01
申请号：US12317855
申请日：2008-12-30
申请人： Anand Deshpande , Venkat Natarajan , Ashok Kabadi , Vittal Kini
发明人： Anand Deshpande , Venkat Natarajan , Ashok Kabadi , Vittal Kini
IPC分类号： H05K7/20
CPC分类号： H01L23/3677 , H01L23/40 , H01L23/427 , H01L2224/73253 , H05K1/0203 , H05K1/141 , H05K3/325 , H05K2201/10159 , H05K2201/10325 , H05K2201/10477 , H05K2201/10719
摘要： In some embodiments, a stacked package assembly may include a first socket defining an interior cavity, a first semiconductor device coupled to the first socket, a second socket positioned within the interior cavity of the first socket, and a second semiconductor device removably coupled to the second socket within the cavity of the first socket. The second socket may be positioned between the first semiconductor device and the second semiconductor device and provide an electrical connection between the first semiconductor device and the second semiconductor device. Other embodiments are disclosed and claimed.
摘要翻译：在一些实施例中，堆叠的包装组件可以包括限定内部空腔的第一插座，耦合到第一插座的第一半导体器件，位于第一插座的内部空腔内的第二插座，以及可移除地耦合到在第一插座的腔内的第二插座。第二插座可以位于第一半导体器件和第二半导体器件之间，并且在第一半导体器件和第二半导体器件之间提供电连接。公开和要求保护其他实施例。

9. 发明授权

US5864659A Computer server with improved reliability, availability and serviceability 失效
标题翻译：计算机服务器具有可靠性，可用性和可维护性
公开(公告)号：US5864659A
公开(公告)日：1999-01-26
申请号：US701193
申请日：1996-08-21
申请人： Vittal Kini
发明人： Vittal Kini
IPC分类号： G06F11/30 , G06F11/28
CPC分类号： G06F11/3006 , G06F11/3055 , G06F11/3065
摘要： An apparatus and method for monitoring and controlling the internal state of a computer system, in particular, a computer server. The computer system includes one or more subsystems. These subsystems provide one or more management signals at a system management slot. The computer system also includes an I/O bus slot coupled to an I/O bus of the computer system. A system management agent is coupled to both the system management slot and the I/O bus slot. The system management agent includes a processor and a memory system coupled to the processor. The system management agent also includes a communications interface coupled to the processor and the memory system.
摘要翻译：一种用于监视和控制计算机系统的内部状态，特别是计算机服务器的装置和方法。计算机系统包括一个或多个子系统。这些子系统在系统管理槽提供一个或多个管理信号。计算机系统还包括耦合到计算机系统的I / O总线的I / O总线插槽。系统管理代理耦合到系统管理槽和I / O总线插槽。系统管理代理包括处理器和耦合到处理器的存储器系统。系统管理代理还包括耦合到处理器和存储器系统的通信接口。

10. 发明授权

US4800532A Circuit arrangement with a processor and at least two read-write memories 失效
标题翻译：具有处理器和至少两个读写存储器的电路布置
公开(公告)号：US4800532A
公开(公告)日：1989-01-24
申请号：US125628
申请日：1987-11-25
申请人： Karl-Heinz Honeck , David Johnson , Manfred Neugebauer , Walter Teutsch , M. Vittal Kini , Steven C. Stacey
发明人： Karl-Heinz Honeck , David Johnson , Manfred Neugebauer , Walter Teutsch , M. Vittal Kini , Steven C. Stacey
IPC分类号： G11C5/14 , G11C13/00
CPC分类号： G11C5/143
摘要： In order for any failure of the power supply unit for two read-write memories which are operable in parallel, not to result in irreversible damage to data, two parallel power supply circuits are provided for the operation of the memories. Each power supply circuit is capable of supplying the operating current of one of the memories and the standby current of the remaining memory. Each of the power supply circuits in the power supply is buffered with capacitors in such a manner that, upon a fault in one of the power supply circuits, the output voltage, as soon as the capacitive buffer declines from a normal operating voltage to a threshold voltage and to a minimum operating voltage, data secure current reducing steps are taken. The capacitive circuits and threshold voltages are selected such that the period of time the voltage takes to decline from the threshold to the minimum operating voltage is longer than the time required to complete the present read-write operation and to save the relevant data into the memory. One of the memories is then put into standby mode by a monitoring device as the output voltage declines to the threshold voltage leaving only one active memory which can be operated from one of the two memory power supply circuits.
摘要翻译：为了并联可操作的两个读写存储器的电源单元的任何故障，不会对数据造成不可逆的损坏，因此为存储器的操作提供两个并联电源电路。每个电源电路能够提供其中一个存储器的工作电流和剩余存储器的待机电流。电源中的每个电源电路用电容器缓冲，使得当电源电路中的一个故障时，输出电压一旦电容缓冲器从正常工作电压下降到阈值电压和最小工作电压，采取数据安全电流降低步骤。选择电容电路和阈值电压使得电压从阈值下降到最小工作电压的时间段长于完成当前读写操作所需的时间并将相关数据保存到存储器中。其中一个存储器随后随着输出电压下降到阈值电压而被置于待机模式，只剩下一个可从两个存储器电源电路之一操作的有效存储器。

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