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1. 发明授权

US08487684B2 Method for buffering clock skew by using a logical effort 有权
标题翻译：通过使用逻辑努力缓冲时钟偏移的方法
公开(公告)号：US08487684B2
公开(公告)日：2013-07-16
申请号：US13155523
申请日：2011-06-08
申请人： Chung-Ying Hsieh , Ming-Hung Chang , Wei Hwang
发明人： Chung-Ying Hsieh , Ming-Hung Chang , Wei Hwang
IPC分类号： G06F1/04 , H03K3/00
CPC分类号： G06F1/10
摘要： A method buffers clock skew by using a logical effort, and is applicable to a clock tree that stays in a strong-inversion region, a moderate-inversion region, or a weak-inversion region. The method includes establishing in the clock tree a temperature sensor and a tunable-width buffer, and establishing width and temperature comparative lists according to a logical effort equation, for the tunable-width buffer to be individually applied to the strong-inversion region, the moderate-inversion region, and the weak-inversion region; selecting one from the width and temperature comparative lists that corresponds to one of the inversion regions in which the clock tree stays, enabling the temperature sensor to sense a temperature, and searching the selected width and temperature comparative list for a width that corresponds to the temperature sensed by the temperature sensor; and enabling the tunable-width buffer to perform a width modulation process according to the searched width.
摘要翻译：一种方法通过使用逻辑努力来缓冲时钟偏移，并且适用于停留在强反转区域，中等反转区域或弱反转区域中的时钟树。该方法包括在时钟树中建立温度传感器和可调宽度缓冲器，并且根据逻辑努力方程建立宽度和温度比较列表，对于可单独应用于强反转区域的可调宽度缓冲器，中等反演区域和弱反演区域; 从与时钟树停留的反转区域中的一个对应的宽度和温度比较列表中选择一个，使得温度传感器能够感测温度，并且在所选择的宽度和温度比较列表中搜索对应于温度的宽度由温度传感器感测; 并且使得可调宽度缓冲器能够根据所搜索的宽度执行宽度调制处理。

2. 发明授权

US08419274B2 Fully-on-chip temperature, process, and voltage sensor system 有权
标题翻译：全面的温度，过程和电压传感器系统
公开(公告)号：US08419274B2
公开(公告)日：2013-04-16
申请号：US12910199
申请日：2010-10-22
申请人： Shi-Wen Chen , Ming-Hung Chang , Wei-Chih Hsieh , Wei Hwang
发明人： Shi-Wen Chen , Ming-Hung Chang , Wei-Chih Hsieh , Wei Hwang
IPC分类号： G01K7/00
CPC分类号： G01K7/01 , G01K2219/00
摘要： A fully on-chip temperature, process, and voltage sensor includes a voltage sensor, a process sensor and a temperature sensor. The temperature sensor includes a bias current generator, a ring oscillator, a fixed pulse generator, an AND gate, and a first counter. The bias current generator generates an output current related to temperature according to the operating voltage of chip. The ring oscillator generates an oscillation signal according to the output current. The fixed pulse generator generates a fixed pulse signal. The AND gate is connected to the ring oscillator and the fixed pulse generator for performing a logic AND operation on the oscillation signal and the fixed pulse signal, and generating a temperature sensor signal.
摘要翻译：完全片上的温度，过程和电压传感器包括电压传感器，过程传感器和温度传感器。温度传感器包括偏置电流发生器，环形振荡器，固定脉冲发生器，与门和第一计数器。偏置电流发生器根据芯片的工作电压产生与温度相关的输出电流。环形振荡器根据输出电流产生振荡信号。固定脉冲发生器产生固定的脉冲信号。与门连接到环形振荡器和固定脉冲发生器，用于对振荡信号和固定脉冲信号进行逻辑与运算，并产生温度传感器信号。

3. 发明授权

US08385149B2 Gate oxide breakdown-withstanding power switch structure 有权
标题翻译：栅极氧化物击穿电源开关结构
公开(公告)号：US08385149B2
公开(公告)日：2013-02-26
申请号：US13075682
申请日：2011-03-30
申请人： Hao-I Yang , Ching-Te Chuang , Wei Hwang
发明人： Hao-I Yang , Ching-Te Chuang , Wei Hwang
IPC分类号： G11C5/14
CPC分类号： G11C11/417
摘要： The present invention proposes a gate oxide breakdown-withstanding power switch structure, which is connected with an SRAM and comprises a first CMOS switch and a second CMOS switch respectively having different gate-oxide thicknesses or different threshold voltages. The CMOS switch, which has a normal gate-oxide thickness or a normal threshold voltage, provides current for the SRAM to wake up the SRAM from a standby or sleep mode to an active mode. The CMOS switch, which has a thicker gate-oxide thickness or a higher threshold voltage, provides current for the SRAM to work in an active mode. The present invention prevents a power switch from gate-oxide breakdown lest noise margin, stabilization and performance of SRAM be affected.
摘要翻译：本发明提出一种栅极氧化物击穿电源开关结构，其与SRAM连接，并且包括分别具有不同栅极氧化物厚度或不同阈值电压的第一CMOS开关和第二CMOS开关。具有正常栅极氧化物厚度或正常阈值电压的CMOS开关为SRAM提供电流，以将SRAM从待机或睡眠模式唤醒至活动模式。具有更厚栅极氧化物厚度或更高阈值电压的CMOS开关为SRAM提供工作在主动模式的电流。本发明防止电源开关从栅极氧化层击穿，以免噪声容限，SRAM的稳定性和性能受到影响。

4. 发明授权

US08345504B2 Data-aware dynamic supply random access memory 有权
标题翻译：数据感知动态供应随机存取存储器
公开(公告)号：US08345504B2
公开(公告)日：2013-01-01
申请号：US13009240
申请日：2011-01-19
申请人： Ching-Te Chuang , Hao-I Yang , Yi-Wei Lin , Wei Hwang , Wei-Chiang Shih , Chia-Cheng Chen
发明人： Ching-Te Chuang , Hao-I Yang , Yi-Wei Lin , Wei Hwang , Wei-Chiang Shih , Chia-Cheng Chen
IPC分类号： G11C11/40
CPC分类号： G11C11/413 , G11C11/412
摘要： A Random Access Memory (RAM) with a plurality of cells is provided. In an embodiment, the cells of a same column are coupled to a same pair of bit-lines and are associated to a same power controller. Each cell has two inverters; the power controller has two power-switches. For the cells of the same column, the two power-switches respectively perform independent supply voltage controls for the two inverters in each cell according to data-in voltages of the bit-lines during Write operation.
摘要翻译：提供具有多个单元的随机存取存储器（RAM）。在一个实施例中，同一列的单元耦合到同一对位线并且与相同的功率控制器相关联。每个电池有两个逆变器; 电源控制器有两个电源开关。对于同一列的单元，两个电源开关根据写操作期间位线的数据输入电压分别对每个单元中的两个反相器执行独立的电源电压控制。

5. 发明申请

US20120230086A1 STATIC RANDOM ACCESS MEMORY CELL AND METHOD OF OPERATING THE SAME 有权
标题翻译：静态随机访问存储单元及其操作方法
公开(公告)号：US20120230086A1
公开(公告)日：2012-09-13
申请号：US13096796
申请日：2011-04-28
申请人： Yi-Te Chiu , Ming-Hung Chang , Hao-I Yang , Wei Hwang
发明人： Yi-Te Chiu , Ming-Hung Chang , Hao-I Yang , Wei Hwang
IPC分类号： G11C11/00
CPC分类号： G11C11/412
摘要： A static random access memory cell includes a latch unit. The latch unit includes a bi-inverting circuit and a switching circuit. The bi-inverting circuit has a first terminal and a second terminal. The switching circuit is electrically connected between the first terminal and the second terminal, wherein when the switching circuit is turned on, the switching circuit forms a feedback between the first terminal and the second terminal for latching the latch unit; and when the switching circuit is turned off, the feedback is removed to cause the SRAM cell to write a data bit to the latch unit.
摘要翻译：静态随机存取存储单元包括一个锁存单元。锁存单元包括双向电路和开关电路。双向电路具有第一端子和第二端子。开关电路电连接在第一端子和第二端子之间，其中当开关电路导通时，开关电路在第一端子和第二端子之间形成用于锁存闩锁单元的反馈; 并且当切换电路关闭时，消除反馈以使SRAM单元向锁存单元写入数据位。

6. 发明授权

US08237477B1 Programmable clock generator used in dynamic-voltage-and-frequency-scaling (DVFS) operated in sub- and near- threshold region 有权
标题翻译：用于动态电压和频率缩放（DVFS）的可编程时钟发生器用于子阈值和近阈值区域
公开(公告)号：US08237477B1
公开(公告)日：2012-08-07
申请号：US13067232
申请日：2011-05-18
申请人： Chung-Ying Hsieh , Ming-Hung Chang , Wei Hwang
发明人： Chung-Ying Hsieh , Ming-Hung Chang , Wei Hwang
IPC分类号： H03L7/06
CPC分类号： H03L7/0816 , H03L1/00 , H03L7/0814
摘要： A programmable clock generator, which is used in dynamic-voltage-and-frequency-scaling (DVFS) operated in Sub- and Near-Threshold region. The programmable clock generator includes first pulse generating unit and a pulse multiplier. A first counter is configured to generate a first counting signal, so as to control the phase detector comparing the phase difference between a first pulse signal and a second pulse signal. A first control signal is transmitted by a control unit in accordance with a phase difference signal, and the phase of the second pulse signal is adjusted by a lock-in delay unit, so that a predetermined phase is generated between the first pulse signal and the second pulse signal. The PVT variation may be compensated by the programmable clock generator during the sub threshold region. Therefore, the period of reference clock is in the locking range of lock-in delay line.
摘要翻译：可编程时钟发生器，用于在子阈值和近阈值区域工作的动态电压和频率缩放（DVFS）。可编程时钟发生器包括第一脉冲发生单元和脉冲乘法器。第一计数器被配置为产生第一计数信号，以便控制相位检测器比较第一脉冲信号和第二脉冲信号之间的相位差。第一控制信号由控制单元根据相位差信号发送，第二脉冲信号的相位由锁定延迟单元调整，使得在第一脉冲信号和第二脉冲信号之间产生预定的相位第二脉冲信号。 PVT变化可以由子阈值区域内的可编程时钟发生器补偿。因此，参考时钟周期处于锁定延迟线的锁定范围。

7. 发明授权

US07738275B2 Leakage current cut-off device for ternary content addressable memory 有权
标题翻译：用于三元内容可寻址存储器的泄漏电流截止装置
公开(公告)号：US07738275B2
公开(公告)日：2010-06-15
申请号：US12007826
申请日：2008-01-16
申请人： Po-Tsang Huang , Wen-Yen Liu , Wei Hwang
发明人： Po-Tsang Huang , Wen-Yen Liu , Wei Hwang
IPC分类号： G11C7/00
CPC分类号： G11C15/04
摘要： A leakage current cut-off device for a ternary content addressable memory is provided. The storage cell of a ternary content addressable memory may be in the active mode, data-retention mode and cut-off mode. This invention applies a multi-mode data retention power gating device to the storage cell of the ternary content addressable memory to reduce the leakage current through the storage cell in the data-retention mode and the cut-off mode, and support the full speed operation in the active mode.
摘要翻译：提供一种用于三元内容可寻址存储器的漏电流截止装置。三元内容可寻址存储器的存储单元可以处于活动模式，数据保持模式和截止模式。本发明将多模式数据保持电源门控装置应用于三元内容可寻址存储器的存储单元，以减少在数据保持模式和截止模式下通过存储单元的泄漏电流，并且支持全速操作处于活动模式。

8. 发明授权

US07525827B2 Stored don't-care based hierarchical search-line scheme 有权
标题翻译：存储不进行基于分层的搜索线方案
公开(公告)号：US07525827B2
公开(公告)日：2009-04-28
申请号：US11675386
申请日：2007-02-15
申请人： Shu-Wei Chang , Wei Hwang , Ming-Hung Chang , Po-Tsang Huang
发明人： Shu-Wei Chang , Wei Hwang , Ming-Hung Chang , Po-Tsang Huang
IPC分类号： G11C15/00
CPC分类号： G11C15/04
摘要： In the proposed stored don't-care hierarchical search-line scheme, a content-addressable memory (CAM) is divided into several blocks. Each block contains a plurality of local search-lines, a global search-line, a buffer and a memory memory cell. Data are stored in the blocks in order according to the length of the prefix. Data with the longest prefix is stored at the bottommost, and its don't-care state is used as the control signal of the buffer to control whether to transfer the data on the global search-line to the local search-line or not. The local search-line then transfer the value into the memory cell. There is no complex control circuit and extra storage device needed. Moreover, because the control signal directly comes from the don't-care state, power consumption on search-lines can be effectively reduced with no increase of search delay.
摘要翻译：在所提出的不存在的分层搜索线方案中，内容寻址存储器（CAM）被分成几个块。每个块包含多个本地搜索行，全局搜索行，缓冲器和存储器存储单元。数据按照前缀的长度顺序存储在块中。具有最长前缀的数据被存储在最底部，并且其不关心状态被用作缓冲器的控制信号，以控制是否将全局搜索行上的数据传送到本地搜索行。然后本地搜索行将值传送到存储单元。没有复杂的控制电路和额外的存储设备需要。此外，由于控制信号直接来自不注意状态，因此可以有效地减少搜索线上的功耗，而不增加搜索延迟。

9. 发明授权

US07259598B2 Clock switching circuit 有权
公开(公告)号：US07259598B2
公开(公告)日：2007-08-21
申请号：US11406312
申请日：2006-04-19
申请人： Jian-Hua Wu , Wei Hwang
发明人： Jian-Hua Wu , Wei Hwang
IPC分类号： G06F1/08 , H03K17/00
CPC分类号： G06F1/08 , G06F1/12
摘要： The present invention discloses a clock switching circuit, which comprises: a clock generator, receiving two different clock signals; a logic gate, coupled to an enable-signal generator and an output-clock generator, wherein during clock switching, the logic gate turns off output clock according to the signal edges of those two clock signals to avoid the problems of clock glitch and timing insufficiency, and the logic gate will not restore clock output until an appropriate timing occurs.

10. 发明授权

US06511882B1 Method for preventing the leakage path in embedded non-volatile memory 有权
标题翻译：防止嵌入式非易失性存储器中泄漏路径的方法
公开(公告)号：US06511882B1
公开(公告)日：2003-01-28
申请号：US09990287
申请日：2001-11-23
申请人： Tung-Cheng Kuo , Shou-Wei Hwang , Chien-Hung Liu , Shyi-Shuh Pan
发明人： Tung-Cheng Kuo , Shou-Wei Hwang , Chien-Hung Liu , Shyi-Shuh Pan
IPC分类号： H01L218247
CPC分类号： H01L27/11568 , H01L27/105 , H01L27/11573
摘要： A method for forming an embedded non-volatile memory is disclosed. The embedded non-volatile memory, comprises memory array and logic device area, is formed on a substrate where an oxide/nitride/oxide (ONO) layer on a memory array, a gate oxide layer on a logic device area. The method is that transistors of memory array and transistors of logic device area are formed by two separately photolithography processes. In memory array, the pitch between the poly gate electrodes is equivalent and has wider spacer width. In logic device area, the pitch between the poly gate electrodes is different and has suitable spacer width. According to above-mentioned, by using separated spacer width in memory array and logic device area can avoid the leakage path between bit line to bit line in subsequently self-aligned salicide process.
摘要翻译：公开了一种用于形成嵌入式非易失性存储器的方法。在存储器阵列上的氧化物/氮化物/氧化物（ONO）层，逻辑器件区域上的栅极氧化物层的衬底上形成包括存储器阵列和逻辑器件区域的嵌入式非易失性存储器。该方法是存储器阵列的晶体管和逻辑器件区域的晶体管由两个分开的光刻工艺形成。在存储器阵列中，多晶硅栅电极之间的间距是等效的并且具有更宽的间隔物宽度。在逻辑器件区域中，多晶硅栅极之间的间距是不同的并且具有合适的间隔物宽度。根据上述，通过在存储器阵列中使用分离的间隔物宽度，并且逻辑器件区域可以避免随后自对准自对准过程中位线与位线之间的泄漏路径。

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