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    • 6. 发明授权
    • Semiconductor yield management system and method
    • 半导体产出管理系统及方法
    • US08380472B2
    • 2013-02-19
    • US12150676
    • 2008-04-29
    • Weidong WangJonathan B. Buckheit
    • Weidong WangJonathan B. Buckheit
    • G06G7/48
    • H01L22/20
    • A system and method for yield management are disclosed wherein a data set containing one or more prediction variable values and one or more response variable values is input into the system. The system can process the input data set to remove prediction variables with missing values and data sets with missing values based on a tiered splitting method to maximize usage of all valid data points. The processed data can then be used to generate a model that may be a decision tree. The system can accept user input to modify the generated model. Once the model is complete, one or more statistical analysis tools can be used to analyze the data and generate a list of the key yield factors for the particular data set.
    • 公开了一种用于产量管理的系统和方法,其中将包含一个或多个预测变量值和一个或多个响应变量值的数据集输入到系统中。 系统可以处理输入数据集,以基于分层分割方法删除具有缺失值的预测变量和具有缺失值的数据集,以最大化所有有效数据点的使用。 然后,处理的数据可以用于生成可以是决策树的模型。 系统可以接受用户输入修改生成的模型。 一旦模型完成,就可以使用一个或多个统计分析工具来分析数据并生成特定数据集的关键产出因子的列表。
    • 7. 发明授权
    • Analysis techniques for multi-level memory
    • 多级内存分析技术
    • US07954018B2
    • 2011-05-31
    • US11701700
    • 2007-02-02
    • Tom T. HoJonathan B. BuckheitWeidong Wang
    • Tom T. HoJonathan B. BuckheitWeidong Wang
    • G11C29/00
    • G11C29/56G11C29/10G11C29/56008
    • A system and method for defect analysis of multi-level memory cell devices and embedded multi-level memory in system-on-chip integrated circuits are disclosed wherein a defect data set is input into the system. When a defect data set is received, an automated test engineering system running a memory test program analyzes the defect data set to generate one or more fail bit locations and one or more fail states of the memory. The multi-level memory defect analysis system and method then classify failed bits or patterns comprising a vertical fail pattern, whereby after being classified, each memory cell failure vertical fail pattern has three data attributes comprising fail type, a number of fail bits/states, and a sequence of the fail states. The vertical fail pattern may comprise a single fail state or multi-state fail. The multi-state fail may be a continuous-states fail, discontinuous-states fail, or all-state fail. The multi-level memory defect analysis system and method may additionally enable classification of failed bits or patterns comprising a lateral fail pattern. The lateral fail pattern may be a gradual fail pattern, periodic fail pattern, or random fail pattern.
    • 公开了一种用于系统级芯片集成电路中的多级存储单元器件和嵌入式多级存储器的缺陷分析的系统和方法,其中将缺陷数据集输入到系统中。 当接收到缺陷数据集时,运行内存测试程序的自动测试工程系统分析缺陷数据集以生成一个或多个故障位位置和存储器的一个或多个故障状态。 多级存储器缺陷分析系统和方法然后对包括垂直故障模式的故障位或模式进行分类,由此在分类之后,每个存储单元故障垂直故障模式具有包括故障类型,多个故障位/状态的三个数据属性, 和一系列的失败状态。 垂直故障模式可能包含单个故障状态或多状态故障。 多状态失败可能是连续状态失败,不连续状态失败或全状态失败。 多级存储器缺陷分析系统和方法还可以使得能够对包括横向失效模式的故障位或模式进行分类。 横向失效模式可能是逐渐失败模式,周期性失败模式或随机失败模式。