专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20210004328A1 HARDWARE/SOFTWARE CO-OPTIMIZATION TO IMPROVE PERFORMANCE AND ENERGY FOR INTER-VM COMMUNICATION FOR NFVS AND OTHER PRODUCER-CONSUMER WORKLOADS 有权
公开(公告)号：US20210004328A1
公开(公告)日：2021-01-07
申请号：US17027248
申请日：2020-09-21
申请人： Ren Wang , Andrew J. Herdrich , Yen-cheng Liu , Herbert H. Hum , Jong Soo Park , Christopher J. Hughes , Namakkal N. Venkatesan , Adrian C. Moga , Aamer Jaleel , Zeshan A. Chishti , Mesut A. Ergin , Jr-shian Tsai , Alexander W. Min , Tsung-yuan C. Tai , Christian Maciocco , Rajesh Sankaran
发明人： Ren Wang , Andrew J. Herdrich , Yen-cheng Liu , Herbert H. Hum , Jong Soo Park , Christopher J. Hughes , Namakkal N. Venkatesan , Adrian C. Moga , Aamer Jaleel , Zeshan A. Chishti , Mesut A. Ergin , Jr-shian Tsai , Alexander W. Min , Tsung-yuan C. Tai , Christian Maciocco , Rajesh Sankaran
IPC分类号： G06F12/0842 , G06F12/0831 , G06F12/0893 , G06F12/109 , G06F12/0813 , G06F9/455
摘要： Methods and apparatus implementing Hardware/Software co-optimization to improve performance and energy for inter-VM communication for NFVs and other producer-consumer workloads. The apparatus include multi-core processors with multi-level cache hierarchies including and L1 and L2 cache for each core and a shared last-level cache (LLC). One or more machine-level instructions are provided for proactively demoting cachelines from lower cache levels to higher cache levels, including demoting cachelines from L1/L2 caches to an LLC. Techniques are also provided for implementing hardware/software co-optimization in multi-socket NUMA architecture system, wherein cachelines may be selectively demoted and pushed to an LLC in a remote socket. In addition, techniques are disclosure for implementing early snooping in multi-socket systems to reduce latency when accessing cachelines on remote sockets.

2. 发明申请

US20200327084A1 FLEXIBLE ON-DIE FABRIC INTERFACE 审中-公开
公开(公告)号：US20200327084A1
公开(公告)日：2020-10-15
申请号：US16914327
申请日：2020-06-27
申请人： Swadesh Choudhary , Robert G. Blankenship , Siva Prasad Gadey , Sailesh Kumar , Vinit Mathew Abraham , Yen-Cheng Liu
发明人： Swadesh Choudhary , Robert G. Blankenship , Siva Prasad Gadey , Sailesh Kumar , Vinit Mathew Abraham , Yen-Cheng Liu
IPC分类号： G06F13/40
摘要： An interface for coupling an agent to a fabric supports a set of coherent interconnect protocols and includes a global channel to communicate control signals to support the interface, a request channel to communicate messages associated with requests to other agents on the fabric, a response channel to communicate responses to other agents on the fabric, and a data channel to couple to communicate messages associated with data transfers to other agents on the fabric, where the data transfers include payload data.

3. 发明申请

US20180101502A1 MULTIPLE DIES HARDWARE PROCESSORS AND METHODS 审中-公开
公开(公告)号：US20180101502A1
公开(公告)日：2018-04-12
申请号：US15721822
申请日：2017-09-30
申请人： NEVINE NASSIF , YEN-CHENG LIU , KRISHNAKANTH V. SISTLA , GERALD PASDAST , SIVA SOUMYA EACHEMPATI , TEJPAL SINGH , ANKUSH VARMA , MAHESH K. KUMASHIKAR , SRIKANTH NIMMAGADDA , CARLETON L. MOLNAR , VEDARAMAN GEETHA , JEFFREY D. CHAMBERLAIN , WILLIAM R. HALLECK , GEORGE Z. CHRYSOS , JOHN R. AYERS , DHEERAJ R. SUBBAREDDY
发明人： NEVINE NASSIF , YEN-CHENG LIU , KRISHNAKANTH V. SISTLA , GERALD PASDAST , SIVA SOUMYA EACHEMPATI , TEJPAL SINGH , ANKUSH VARMA , MAHESH K. KUMASHIKAR , SRIKANTH NIMMAGADDA , CARLETON L. MOLNAR , VEDARAMAN GEETHA , JEFFREY D. CHAMBERLAIN , WILLIAM R. HALLECK , GEORGE Z. CHRYSOS , JOHN R. AYERS , DHEERAJ R. SUBBAREDDY
IPC分类号： G06F15/78 , G06F15/173 , G06F9/50 , G06F9/38
CPC分类号： G06F15/7889 , G06F1/10 , G06F9/3869 , G06F9/5038 , G06F15/167 , G06F15/17312
摘要： Methods and apparatuses relating to hardware processors with multiple interconnected dies are described. In one embodiment, a hardware processor includes a plurality of physically separate dies, and an interconnect to electrically couple the plurality of physically separate dies together. In another embodiment, a method to create a hardware processor includes providing a plurality of physically separate dies, and electrically coupling the plurality of physically separate dies together with an interconnect.

4. 发明申请

US20150178202A1 METHOD AND APPARATUS FOR CACHE LINE WRITE BACK OPERATION 有权
标题翻译：高速缓存行写回操作的方法和装置
公开(公告)号：US20150178202A1
公开(公告)日：2015-06-25
申请号：US14137432
申请日：2013-12-20
申请人： Rajesh M. Sankaran , Neil M. Schaper , Joseph Nuzman , Larisa Novakovsky , Yen-Cheng Liu , Gilbert Neiger , Raj K. Ramanujan
发明人： Rajesh M. Sankaran , Neil M. Schaper , Joseph Nuzman , Larisa Novakovsky , Yen-Cheng Liu , Gilbert Neiger , Raj K. Ramanujan
IPC分类号： G06F12/08
CPC分类号： G06F12/0811 , G06F12/0804 , G06F12/0815 , G06F12/0831 , G06F2212/1032 , G06F2212/222
摘要： An apparatus and method are described for performing a cache line write back operation. For example, one embodiment of a method comprises: initiating a cache line write back operation directed to a particular linear address; determining if a dirty cache line identified by the linear address exists at any cache of a cache hierarchy comprised of a plurality of cache levels; writing back the dirty cache line to memory if the dirty cache line exists in one of the caches; and responsively maintaining or placing the dirty cache line in an exclusive state in at least a first cache of the hierarchy.
摘要翻译：描述了用于执行高速缓存行回写操作的装置和方法。例如，方法的一个实施例包括：发起针对特定线性地址的高速缓存行回写操作; 确定由线性地址识别的脏高速缓存行是否存在于由多个高速缓存级别组成的高速缓存层级的任何高速缓存上; 如果脏缓存行存在于其中一个缓存中，则将脏缓存行写回内存; 以及响应地将所述脏高速缓存行维持或置于所述层次结构的至少第一高速缓存中的排他状态。

5. 发明申请

US20130151930A1 Injecting A Data Error Into A Writeback Path To Memory 有权
标题翻译：将数据错误注入到内存的回写路径中
公开(公告)号：US20130151930A1
公开(公告)日：2013-06-13
申请号：US13323405
申请日：2011-12-12
申请人： Theodros Yigzaw , Yen-Cheng Liu , Mohan J. Kumar , Jose A. Vargas
发明人： Theodros Yigzaw , Yen-Cheng Liu , Mohan J. Kumar , Jose A. Vargas
IPC分类号： G06F11/10
CPC分类号： G06F11/2236
摘要： In one embodiment, a processor includes error injection circuitry separate and independent of debug circuitry of the processor. This circuitry can be used by a software developer to seed errors into a write-back path to system memory to emulate errors for purposes of validation of error recovery code of the software. The circuitry can include a register to store an address within the system memory at which an error is to be injected, a detection logic to detect when an instruction associated with the address is issued, and injection logic to cause the error to be injected into the address within the system memory responsive to the detection of the instruction. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，处理器包括与处理器的调试电路分开且独立的错误注入电路。软件开发人员可以使用该电路将错误引入到系统内存的回写路径中，以便为验证软件的错误恢复代码而进行模拟。该电路可以包括一个寄存器，用于存储系统存储器中要注入错误的地址;检测逻辑，用于检测何时发出与该地址相关联的指令;以及注入逻辑，以使该错误被注入到响应于指令的检测而在系统存储器内的地址。描述和要求保护其他实施例。

6. 发明申请

US20080162972A1 OPTIMIZING POWER USAGE BY FACTORING PROCESSOR ARCHITECUTRAL EVENTS TO PMU 有权
标题翻译：通过处理器将建筑事件优化给PMU
公开(公告)号：US20080162972A1
公开(公告)日：2008-07-03
申请号：US11618477
申请日：2006-12-29
申请人： Yen-Cheng Liu , P. Keong Or , Krishnakanth Sistia , Ganapati Srinivasa
发明人： Yen-Cheng Liu , P. Keong Or , Krishnakanth Sistia , Ganapati Srinivasa
IPC分类号： G06F1/32
CPC分类号： G06F1/3243 , G06F1/206 , G06F1/3203 , G06F1/3206 , G06F1/324 , G06F1/3275 , G06F1/3287 , G06F12/0811 , G06F15/80 , G06F2212/283 , G11C7/1072 , G11C7/1075 , Y02D10/16
摘要： A method and apparatus to monitor architecture events is disclosed. The architecture events are linked together via a push bus mechanism with each architectural event having a designated time slot. There is at least one branch of the push bus in each core. Each branch of the push bus may monitor one core with all the architectural events. All the data collected from the events by the push bus is then sent to a power control unit.
摘要翻译：公开了一种监视架构事件的方法和装置。架构事件通过推送总线机制链接在一起，每个架构事件都具有指定的时隙。在每个核心中至少有一个分支的推送总线。推送总线的每个分支可以监视一个核心与所有的架构事件。然后将通过推送总线从事件收集的所有数据发送到电源控制单元。

7. 发明申请

US20190236038A1 BUFFERED INTERCONNECT FOR HIGHLY SCALABLE ON-DIE FABRIC 审中-公开
公开(公告)号：US20190236038A1
公开(公告)日：2019-08-01
申请号：US16227364
申请日：2018-12-20
申请人： Swadesh Choudhary , Bahaa Fahim , Doddaballapur Jayashimha , Jeffrey Chamberlain , Yen-Cheng Liu
发明人： Swadesh Choudhary , Bahaa Fahim , Doddaballapur Jayashimha , Jeffrey Chamberlain , Yen-Cheng Liu
IPC分类号： G06F13/20 , G06F13/40
CPC分类号： G06F13/20 , G06F13/4027
摘要： Buffered interconnects for highly scalable on-die fabric and associated methods and apparatus. A plurality of nodes on a die are interconnected via an on-die fabric. The nodes and fabric are configured to implement forwarding of credited messages from source nodes to destination nodes using forwarding paths partitioned into a plurality of segments, wherein separate credit loops are implemented for each segment. Under one fabric configuration implementing an approach called multi-level crediting, the nodes are configured in a two-dimensional grid and messages are forwarded using vertical and horizontal segments, wherein a first segment is between a source node and a turn node in the same row or column and the second segment is between the turn node and a destination node. Under another approach called buffered mesh, buffering and credit management facilities are provided at each node and adjacent nodes are configured to implement credit loops for forwarding messages between the nodes. The fabrics may comprise various topologies, including 2D mesh topologies and ring interconnect structures. Moreover, multi-level crediting and buffered mesh may be used for forwarding messages across dies.

8. 发明申请

US20160283382A1 METHOD, APPARATUS AND SYSTEM FOR OPTIMIZING CACHE MEMORY TRANSACTION HANDLING IN A PROCESSOR 有权
标题翻译：用于优化处理器中的高速缓存存储器交易处理的方法，装置和系统
公开(公告)号：US20160283382A1
公开(公告)日：2016-09-29
申请号：US14669248
申请日：2015-03-26
申请人： Bahaa Fahim , Yen-Cheng Liu , Vedaraman Geetha , Jeffrey D. Chamberlain , Min Huang
发明人： Bahaa Fahim , Yen-Cheng Liu , Vedaraman Geetha , Jeffrey D. Chamberlain , Min Huang
IPC分类号： G06F12/08
CPC分类号： G06F12/0855 , G06F12/0817 , G06F12/0831 , G06F2212/27 , G06F2212/621 , Y02D10/13
摘要： In one embodiment, a processor includes a caching home agent (CHA) coupled to a core and a cache memory and includes a cache controller having a cache pipeline and a home agent having a home agent pipeline. The CHA may: receive, in the home agent pipeline, information from an external agent responsive to a miss for data in the cache memory; issue a global ordering signal from the home agent pipeline to a requester of the data to inform the requester of receipt of the data; and report issuance of the global ordering signal to the cache pipeline, to prevent the cache pipeline from issuance of a global ordering signal to the requester. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，处理器包括耦合到核心和高速缓冲存储器的缓存归属代理（CHA），并且包括具有高速缓存流水线和具有归属代理流水线的归属代理的高速缓存控制器。 CHA可以：在归属代理流程中接收来自外部代理的响应于高速缓冲存储器中的数据的遗漏的信息; 从归属代理流水线向数据的请求者发出全局排序信号，以通知请求者接收数据; 并向缓存流水线报告全局排序信号的发布，以防止缓存流水线向请求者发出全局排序信号。描述和要求保护其他实施例。

9. 发明申请

US20160092366A1 METHOD AND APPARATUS FOR DISTRIBUTED SNOOP FILTERING 有权
标题翻译：用于分布式SNOOP过滤的方法和装置
公开(公告)号：US20160092366A1
公开(公告)日：2016-03-31
申请号：US14497740
申请日：2014-09-26
申请人： Rahul PAL , Ishwar AGARWAL , Yen-Cheng LIU , Joseph NUZMAN , Ashok JAGANNATHAN , Bahaa FAHIM , Nithiyanandan BASHYAM
发明人： Rahul PAL , Ishwar AGARWAL , Yen-Cheng LIU , Joseph NUZMAN , Ashok JAGANNATHAN , Bahaa FAHIM , Nithiyanandan BASHYAM
IPC分类号： G06F12/08
CPC分类号： G06F12/0875 , G06F12/0831 , G06F2212/452
摘要： An apparatus and method are described for distributed snoop filtering. For example, one embodiment of a processor comprises: a plurality of cores to execute instructions and process data; first snoop logic to track a first plurality of cache lines stored in a mid-level cache (“MLC”) accessible by one or more of the cores, the first snoop logic to allocate entries for cache lines stored in the MLC and to deallocate entries for cache lines evicted from the MLC, wherein at least some of the cache lines evicted from the MLC are retained in a level 1 (L1) cache; and second snoop logic to track a second plurality of cache lines stored in a non-inclusive last level cache (NI LLC), the second snoop logic to allocate entries in the NI LLC for cache lines evicted from the MLC and to deallocate entries for cache lines stored in the MLC, wherein the second snoop logic is to store and maintain a first set of core valid bits to identify cores containing copies of the cache lines stored in the NI LLC.
摘要翻译：描述了一种用于分布式监听过滤的设备和方法。例如，处理器的一个实施例包括：执行指令和处理数据的多个核; 第一侦听逻辑，用于跟踪存储在由一个或多个核可访问的中级高速缓存（“MLC”）中的第一多个高速缓存行，所述第一侦听逻辑用于为存储在所述MLC中的高速缓存行分配条目，并且取消分配条目对于从MLC移出的高速缓存行，其中从MLC中逐出的至少一些高速缓存行保留在级别1（L1）高速缓存中; 和第二窥探逻辑，用于跟踪存储在非包容性最后一级高速缓存（NI LLC）中的第二多个高速缓存行，所述第二监听逻辑用于在所述NI LLC中分配用于从所述MLC驱逐的高速缓存行的条目，并且取消分配用于高速缓存的条目存储在MLC中的行，其中第二侦听逻辑将存储和维护第一组核心有效位以识别包含存储在NI LLC中的高速缓存行的副本的内核。

10. 发明申请

US20160012010A1 METHOD, APPARATUS AND SYSTEM FOR MODULAR ON-DIE COHERENT INTERCONNECT 有权
标题翻译：方法，装置和系统的模块化在线互连互连
公开(公告)号：US20160012010A1
公开(公告)日：2016-01-14
申请号：US14707656
申请日：2015-05-08
申请人： Krishnakumar GANAPATHY , Yen-Cheng LIU , Antonio JUAN , Steven R. PAGE , Jeffrey D. CHAMBERLAIN , Pau CABRE , Bahaa FAHIM , Gunnar GAUBATZ
发明人： Krishnakumar GANAPATHY , Yen-Cheng LIU , Antonio JUAN , Steven R. PAGE , Jeffrey D. CHAMBERLAIN , Pau CABRE , Bahaa FAHIM , Gunnar GAUBATZ
IPC分类号： G06F15/78 , G06F5/06 , G06F13/42 , G06F13/40
CPC分类号： G06F13/4022 , G06F9/4411 , G06F13/4036 , G06F13/4068 , G06F13/4282 , G06F15/7825
摘要： In an embodiment, an apparatus comprises: a first component to perform coherent operations; and a coherent fabric logic coupled to the first component via a first component interface. The coherent fabric logic may be configured to perform full coherent fabric functionality for coherent communications between the first component and a second component coupled to the coherent fabric logic. The first component may include a packetization logic to communicate packets with the coherent fabric logic, but not include coherent interconnect interface logic to perform coherent fabric functionality. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，一种装置包括：执行相干操作的第一组件; 以及经由第一组件接口耦合到第一组件的相干结构逻辑。相干结构逻辑可以被配置为执行完整的相干结构功能，用于第一组件和耦合到相干结构逻辑的第二组件之间的相干通信。第一组件可以包括用于与分组结构逻辑通信分组的分组化逻辑，但不包括用于执行相干结构功能的相干互连接口逻辑。描述和要求保护其他实施例。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式