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1. 发明专利

JP2017091432A 辞書検索方法および装置审中-公开
公开(公告)号：JP2017091432A
公开(公告)日：2017-05-25
申请号：JP2015224490
申请日：2015-11-17
申请人：日本電信電話株式会社 , Nippon Telegr & Teleph Corp , 学校法人早稲田大学 , Waseda Univ
发明人： AOKI TAKASHI , HATANO TAKAHIRO , OTSUKA TAKUYA , MIYAZAKI AKIHIKO , SHIMAZAKI KENTA , TOGAWA NOZOMI , PARK YONG-JIN , TSUDA TOSHITAKA
IPC分类号： G06F17/30
摘要：【課題】多数の衝突登録文字列が登録されていても短時間で検索文字列を検索する。【解決手段】ハッシュ値ごとに、登録文字列のうち当該ハッシュ値を有する唯一の登録文字列、または、登録文字列のうち当該ハッシュ値を共有する複数の衝突登録文字列をノードとする平衡2分探索木のうちルートノードを参照するための参照先ポインタ値が登録されているハッシュテーブル11Aと、衝突登録文字列と当該衝突登録文字列を識別するためのインデクス値とが、当該衝突登録文字列のハッシュ値に関する平衡2分探索木のノードとして、規定の文字整列順序に基づいて登録されている平衡2分探索木テーブル11Bとを辞書11に設け、検索時において、検索文字列の検索ハッシュ値に対応する平衡2分探索木が構築されている場合には、辞書探索処理部14により、対応する平衡2分探索木から検索文字列を探索する。【選択図】図1

2. 发明专利

JPS59105712A Digital filter 失效
标题翻译：数字滤波器
公开(公告)号：JPS59105712A
公开(公告)日：1984-06-19
申请号：JP21597582
申请日：1982-12-09
申请人： Fujitsu Ltd , Nippon Telegr & Teleph Corp
发明人： MATSUDA KIICHI , TSUDA TOSHITAKA , OKAZAKI TAKESHI , KURODA HIDEO , TAKEGAWA NAOKI
IPC分类号： H03H17/00 , H03H17/06
CPC分类号： H03H17/0621
摘要： PURPOSE:To eliminate the need for high-speed processing for conversion into signals having different sampling frequencies by providing a coefficient control means which produces an output after selecting the coefficient of a digital filter and then multiplying this coefficient by the output of a data series speed converting means and an arithmetic means which produces an output with addition of the result of said multiplication. CONSTITUTION:Flip-flops (FF) D-1-D-5 and D-6-D-10 are set opposite to a data series speed converting part 11. Multipliers 21-1-21-5 are set opposite to a coefficient control part 12, and an adder 22 is set opposite to an arithmetic part 13 respectively. The input data are successively read into FFs D-1-D-5 by an f1 clock, and the output data of the FFs D-1-D-5 are read in parallel to FFs D6-1-D-10 by an f2 clock. The output data FFs D-6-D-10 are multiplied by the coefficient through multipliers 21-1-21-5 in response to the control signal. The outputs of the multipliers 21-1-21-5 are added together by the adder 22. Thus the output data subjected to a desired frequency conversion is obtained as a result of addition.
摘要翻译：目的：通过提供在选择数字滤波器的系数后产生输出的系数控制装置，然后将该系数乘以数据串行速度的输出，消除对用于转换成具有不同采样频率的信号的高速处理的需要转换装置和运算装置，其产生具有所述相乘结果的输出。构成：触发器（FF）D-1-D-5和D-6-D-10被设置为与数据串转换部分11相对。乘法器21-1-21-5被设置为与系数控制部分12和加法器22分别设置为与算术部分13相对。输入数据通过f1时钟连续地读入FF-D-1-D-5，并且将FF D-1-D-5的输出数据与FF6D-D-10并行读取f2 时钟。响应于控制信号，输出数据FF D-6-D-10乘以系数通过乘法器21-1-21-5。乘法器21-1-21-5的输出由加法器22相加在一起。因此，作为相加的结果，获得进行所需频率转换的输出数据。

3. 发明专利

JPS594333A Burst detection circuit 失效
标题翻译： BURST检测电路
公开(公告)号：JPS594333A
公开(公告)日：1984-01-11
申请号：JP11280182
申请日：1982-06-30
申请人： Fujitsu Ltd , Nippon Telegr & Teleph Corp
发明人： NAKAJIYOU TAKAFUMI , TSUDA TOSHITAKA , FUKUDA SETSU , TAMAKI NORIO
IPC分类号： H04B3/06 , H04B3/04
CPC分类号： H04B3/04
摘要： PURPOSE:To detect only a receiving burst without detecting a transmitting burst, by using a frame synchronizing signal of a transmitting burst signal for obtaining information of a transmitting burst period and stopping the detection of burst during this period. CONSTITUTION:The presence or absence of an equalization circuit 1 switching a time constant of the automatic gain control for equalization at the receiving burst period and other periods with a receiving burst control signal, is decided at a decision circuit 2 and inputted to a monostable multivibrator 3. Further, a frequency division circuit 4 generates a signal in response to the transmitting burst period from a frame signal of the transmission signal and a transmission clock and supplies the signal to the monostable multivibrator 3 as a reset signal, and since the monostable multivibrator 3 is reset for the period of the transmission signal, the equalizing circuit 1 detects correctly only the receiving burst with the output of the monostable multivibrator 3.
摘要翻译：目的：通过使用发送脉冲串信号的帧同步信号来检测仅接收脉冲串而不检测发送脉冲串，用于获得发送脉冲串周期的信息，并在该期间停止脉冲串的检测。构成：在判定电路2判定在接收脉冲串周期的其他时段切换用于均衡的自动增益控制的时间常数的均衡电路1的存在与否，并输入到单稳态多谐振荡器此外，分频电路4根据发送信号和发送时钟的帧信号响应于发送脉冲串周期生成信号，并将信号作为复位信号提供给单稳态多谐振荡器3，并且由于单稳态多谐振荡器 3在发送信号的周期中复位，均衡电路1仅使用单稳态多谐振荡器3的输出检测接收脉冲串。

4. 发明专利

JPS5763956A Discrimination circuit used in common for binary code and ternary code 失效
标题翻译：二进制代码和常规代码共同使用的歧视电路
公开(公告)号：JPS5763956A
公开(公告)日：1982-04-17
申请号：JP13865480
申请日：1980-10-06
申请人： Fujitsu Ltd , Nippon Telegr & Teleph Corp
发明人： TSUDA TOSHITAKA , NAKAJIYOU TAKAFUMI , KAMOTO TSUTOMU , OKADA KENJI
IPC分类号： H03M5/16 , H03K19/20 , H04L25/03 , H04L25/06 , H04L25/49
CPC分类号： H04L25/06
摘要： PURPOSE:To use one circuit as both a binary code discriminating circuit and a ternary code discriminating circuit by switching, by varying a control potential by the same LSI chip. CONSTITUTION:Shifting circuits R2-R9 and two differential couples 11 and 12 are provided; and the constant current source composed of transistors TR1 and TR3 is turned on or off by grounding or opening a terminal 13 to turn on or off one differential couple 11 or 12, and AND outputs appear at those two differential couples 11 and 12. Therefore, a discrimination output which corresponds to a binary or ternal signal is obtained at the outputs of the differential couples 11 and 12 according to a potential at the control terminal 13.
摘要翻译：目的：通过改变同一个LSI芯片的控制电位，通过切换将一个电路用作二进制码识别电路和三进制码识别电路。构成：提供了转换电路R2-R9和两个差动对11和12; 并且由晶体管TR1和TR3组成的恒流源通过接地或断开端子13而接通或断开，以接通或断开一个差分耦合11或12，并且在这两个差分耦合11和12处出现AND输出。因此，根据控制端子13的电位，在差动对11和12的输出端获得对应于二进制或三进制信号的鉴别输出。

5. 发明专利

JPS5763910A Differential amplifying circuit 失效
标题翻译：差分放大电路
公开(公告)号：JPS5763910A
公开(公告)日：1982-04-17
申请号：JP13865580
申请日：1980-10-06
申请人： Fujitsu Ltd , Nippon Telegr & Teleph Corp
发明人： NAKAJIYOU TAKAFUMI , TSUDA TOSHITAKA , KAMOTO TSUTOMU , NAGATA YOUICHI
IPC分类号： H03F3/45 , H03K5/02
CPC分类号： H03F3/45071
摘要： PURPOSE:To decrease the number of repeating terminals for connections between an amplifying circuit and external elements, by using only one frequency selecting circuit. CONSTITUTION:A differential amplifier 21 amplifies the difference between an input signal supplied to a terminal 26 and a reference DC voltage applied to a terminal 27. The uninverted output of the amplifier 21 is amplified by the amplifier 30 of a frequency selecting circuit 22. The circuit 22 is provided with capacitors externally. An amplifier 23, on the other hand, is applied with the reference DC voltage from the terminal 27. The amplifier 23 has the same gain as the inphase gain of the amplifier 21 and its output is supplied to an amplifier 24. The amplifier 24 has the same DC input and output characteristics with the amplifier 30. Outputs of the amplifiers 30 and 24 are supplied to a differential amplifier 25, which amplifies the difference between those two inputs to send a pair of an inverted and an uninverted output. Consequently, one passive element part in a frequency selecting circuit is required to decrease the number of external elements, such as the capacitors, thereby decreasing the number of repeating terminals for connections between the amplifying circuit and the external elements.
摘要翻译：目的：通过仅使用一个频率选择电路来减少放大电路和外部元件之间连接的重复端子数量。构成：差分放大器21放大提供给端子26的输入信号和施加到端子27的基准DC电压之间的差。放大器21的未反相输出由频率选择电路22的放大器30放大。电路22在外部设置有电容器。另一方面，放大器23从端子27施加参考DC电压。放大器23具有与放大器21的同相增益相同的增益，并且其输出被提供给放大器24.放大器24具有与放大器30相同的DC输入和输出特性。放大器30和24的输出被提供给差分放大器25，差分放大器25放大这两个输入之间的差以发送一对反相和未反相输出。因此，需要频率选择电路中的一个无源元件部件来减少诸如电容器的外部元件的数量，从而减小放大电路和外部元件之间的连接的重复端子的数量。

6. 发明专利

JPS61103331A Data multiplexer 失效
标题翻译：数据多路复用器
公开(公告)号：JPS61103331A
公开(公告)日：1986-05-21
申请号：JP22548284
申请日：1984-10-26
申请人： Fujitsu Ltd , Nippon Telegr & Teleph Corp
发明人： MATSUDA KIICHI , TSUDA TOSHITAKA , KURODA HIDEO , TAKEGAWA NAOKI
IPC分类号： H04B14/06 , H04J3/16
CPC分类号： H04J3/16
摘要： PURPOSE:To attain a simple multiplex processing without requiring a high speed or a large scale processing circuit by sharing generated data in the unit of prescribe bits and arranging them decentralizingly to a prescribed location. CONSTITUTION:A control circuit 10 gives a signal to a P/S converter 12 to allow the converter 12 to fetch one word of data A, a selector 14 selects the position (a) and a multiplexing circuit 16 multiplexes the signal. The output is transmitted in series on transmission line interface circuits 17a, 17b, fetched by a shift register 18 and the start ends of words are made coincident by a rotor 20. Then an MSB supervisory circuit 26 separates a head bit, codes it at an S/P converter 30 and a decoder 28 extracts other bit.
摘要翻译：目的：为了实现简单的多路复用处理，不需要高速或大规模的处理电路，通过以规定位为单位共享生成数据，并将它们分散布置到规定的位置。构成：控制电路10向P / S转换器12提供信号以允许转换器12取出数据A的一个字，选择器14选择位置（a），复用电路16复用信号。输出在传输线路接口电路17a，17b上串行发送，由移位寄存器18取出，字的起始端由转子20重合。然后MSB监控电路26分离头位， S / P转换器30和解码器28提取其他位。

7. 发明专利

JPS59161132A Variable equalizer 失效
标题翻译：可变均衡器
公开(公告)号：JPS59161132A
公开(公告)日：1984-09-11
申请号：JP3545583
申请日：1983-03-04
申请人： Fujitsu Ltd , Hitachi Ltd , Nec Corp , Nippon Telegr & Teleph Corp , Oki Electric Ind Co Ltd
发明人： TAKADA AKIHIKO , TSUDA TOSHITAKA , KIMURA TADAKATSU , SASAGAWA MASAAKI , SUZUKI TOSHIROU , KURAISHI YOSHIAKI , GUNJI KATSUHIKO
IPC分类号： H04B3/04 , H03H11/02 , H03H11/04 , H04B3/14
CPC分类号： H04B3/145
摘要： PURPOSE:To set optionally a variable width of impedance so that no variation is generated, by dividing a value of an impedance element into plural pieces, and executing the switcing control of a switch so that an output of a variable gain controlling circuit is subjected to prescribed equalizing control. CONSTITUTION:In order to control the gain of equalizing circuits FEG, SEQ, reference voltage V and an equalizing output OUT are compared by a peak value detecting circuit PD, its magnitude is decided, and the continuity of its result is detected by a pulse controlling circuit PC. Subsequently, a pulse from the circuit PC is counted by a counting circuit CNT, and a counting value corresponding to the gain required for the circuit FEQ, SEQ is obtained. An output of this circuit CNT is converted to a logic for switching switches SW11-SW1n and SW21-SW2n provided on the circuits FEQ, SEQ, by a gain controlling circuit LG, and setting of the gain corresponding to the output of the circuit CNT is executed.
摘要翻译：目的：通过将阻抗元件的值除以多个部分，并且执行开关的切换控制，使可变增益控制电路的输出经受规定均衡控制。构成：为了控制均衡电路FEG，SEQ，参考电压V和均衡输出OUT的增益，通过峰值检测电路PD进行比较，确定其幅度，并通过脉冲控制来检测其结果的连续性电路PC。随后，通过计数电路CNT对来自电路PC的脉冲进行计数，并且获得与电路FEQ，SEQ所需的增益相对应的计数值。该电路CNT的输出通过增益控制电路LG转换为设置在电路FEQ，SEQ上的开关SW11-SW1n和SW21-SW2n的逻辑，并且与电路CNT的输出相对应的增益的设定为执行。

8. 发明专利

JPS59160334A Bridged tap equalizing circuit 失效
标题翻译： BRIDGED TAP均衡电路
公开(公告)号：JPS59160334A
公开(公告)日：1984-09-11
申请号：JP3481483
申请日：1983-03-03
申请人： Fujitsu Ltd , Nec Corp , Nippon Telegr & Teleph Corp , Oki Electric Ind Co Ltd
发明人： ISHIKAWA MASAYUKI , KIMURA TADAKATSU , KURAISHI YOSHIAKI , TAKAHASHI YUTAKA , TSUDA TOSHITAKA , FUKAZAWA ATSUSHI
IPC分类号： H04B3/06 , H04B3/23
CPC分类号： H04B3/23
摘要： PURPOSE:To eliminate the need for a large-capacity capacitor for integration which is necessary before by applying digital technology to a bridged tap equivalent circuit. CONSTITUTION:An input signal E0 containing an echo is led to an output terminal E1 through an analog adder 31 and a part of the signal is converted through OP amplifiers 32, 33, and 34 into digital signals E2-E4, which are led to a control part 35. Then, outputs E5 and E6 of this control part are applied to an up/ down counter 36 which accumulates the amounts of echo after one time slot and an up/down counter 37 which accumulates the amount of echo after two time slots. The outputs of both counters 36 and 37 are processed by addition or subtraction through a digital adder and subtracter 38 and then converted by a D/A converter 39 into an analog signal, which is smoothed by a smoothing circuit 40 and then supplied as an echo canceler signal to an adder 31.
摘要翻译：目的：为了消除对用于集成的大容量电容器的需要，在将数字技术应用于桥接抽头等效电路之前是必需的。构成：包含回波的输入信号E0通过模拟加法器31被引导到输出端子E1，并且该信号的一部分通过OP放大器32,33和34被转换成数字信号E2-E4，这些信号被引导到然后，该控制部分的输出E5和E6被加到累积了一个时隙之后的回波量的加/减计数器36和一个在两个时隙之后积累回波量的上/下计数器37 。计数器36和37的输出通过数字加法器和减法器38进行加法或减法处理，然后由D / A转换器39转换成模拟信号，该模拟信号由平滑电路40平滑，然后作为回波提供消除器信号送到加法器31。

9. 发明专利

JPS57125546A Timing pickup circuit 失效
标题翻译：定时取样电路
公开(公告)号：JPS57125546A
公开(公告)日：1982-08-04
申请号：JP1181481
申请日：1981-01-29
申请人： Fujitsu Ltd , Nippon Telegr & Teleph Corp
发明人： YAMAGUCHI KAZUO , TAKAHASHI MOTOHIDE , TSUDA TOSHITAKA , NAKAJIYOU TAKAFUMI , NAGATA YOUICHI , KAMOTO TSUTOMU
IPC分类号： H04L7/02
CPC分类号： H04L7/02
摘要： PURPOSE:To pick up a timing signal from binary or ternary code, by obtaining an output signal of the 1st and 2nd level shift circuits which can change level shift amount and providing the 1st and 2nd differential amplifiers making slice of input waveform through the output signal of the level shift circuits. CONSTITUTION:Differential output signals (a), (b) of an equalizing amplifier circuit are as shown (A) for binary code and as shown (B) for ternary code. A binary/ternary control terminal 18 is grounded for binary code and opened for ternary code. Then, the level shift amount at level shift circuits 11, 12 can be changed. At a binary code, only a differential amplifier 13 is operated and no differential amplifier 14 is operative. Signals c-f respectively level-shfted at the circuits 11, 12 are given to the differential amplifiers 13, 14 and at binary code a signal (g) shown in (C) is outputted from an output terminal 19 and at ternary code, the signal (g) shown in (D) is outputted.
摘要翻译：目的：通过获得能够改变电平偏移量的第一和第二电平移位电路的输出信号并提供第一和第二差分放大器，通过输出信号使输入波形切片，从二进制或三进制码中提取定时信号的电平移位电路。构成：均衡放大器电路的差分输出信号（a），（b）如二进制码所示（A），三进制代码如（B）所示。二进制/三进制控制端子18接地二进制代码并打开三进制代码。然后，能够改变电平移位电路11,12的电平偏移量。在二进制码中，仅操作差分放大器13，并且不使用差分放大器14。在电路11,12上分别电平分配的信号被提供给差分放大器13,14，并且在二进制码中，（C）中所示的信号（g）从输出端子19输出并且以三进制码输出，信号（输出（D）所示的g）。

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