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1. 发明公开

KR20100103418A Flexible packaging for chip-on-chip and package-on-package technologies 有权
标题翻译：芯片芯片和包装封装技术的灵活包装
公开(公告)号：KR20100103418A
公开(公告)日：2010-09-27
申请号：KR20100022244
申请日：2010-03-12
申请人： APPLE INC
发明人： VON KAENEL VINCENT R
IPC分类号： H01L21/77
CPC分类号： H01L25/105 , H01L22/32 , H01L23/49816 , H01L23/49838 , H01L23/50 , H01L24/05 , H01L24/16 , H01L24/24 , H01L24/48 , H01L24/82 , H01L25/0657 , H01L25/18 , H01L25/50 , H01L2224/0401 , H01L2224/13144 , H01L2224/1319 , H01L2224/16225 , H01L2224/24225 , H01L2224/32145 , H01L2224/48227 , H01L2224/82101 , H01L2225/0651 , H01L2225/06517 , H01L2225/06524 , H01L2225/06527 , H01L2225/06551 , H01L2225/06555 , H01L2225/06562 , H01L2225/06596 , H01L2225/1005 , H01L2225/1023 , H01L2225/1058 , H01L2924/00014 , H01L2924/0102 , H01L2924/01079 , H01L2924/07802 , H01L2924/14 , H01L2924/1433 , H01L2924/15173 , H01L2924/15192 , H01L2924/15311 , H01L2924/15312 , H01L2924/15313 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： PURPOSE: A flexible package for a chip-on-chip and a package-on-package technology are provided to minimize a package substrate by eliminating pads and a conductor expanding from the pads. CONSTITUTION: An application integrated circuit(10) includes a core circuit(12), memory controllers(14A, 14B), a first physical layer interface(PHY) circuit(16A) and a second PHY circuit(16B). The first PHY circuit corresponds to a first interface. A second PHY circuit corresponds to the second interface. In the first and second interfaces, the integrated circuit communicates with the outside. First controlled collapse chip connection(C4) bumps(18A, 18B) are formed on the first PHY circuit. Second C4 bumps(18C, 18D) is formed on the second PHY circuit.
摘要翻译：目的：提供用于片上芯片和封装封装技术的灵活封装，通过消除焊盘和从焊盘扩展的导体来最小化封装衬底。构成：应用集成电路（10）包括核心电路（12），存储器控制器（14A，14B），第一物理层接口（PHY）电路（16A）和第二PHY电路（16B）。第一PHY电路对应于第一接口。第二PHY电路对应于第二接口。在第一和第二接口中，集成电路与外部通信。在第一PHY电路上形成第一控制崩溃芯片连接（C4）凸块（18A，18B）。在第二PHY电路上形成第二C4凸块（18C，18D）。

2. 发明专利

JP2010219539A Flexible packaging for chip-on-chip and package-on-package technologies 审中-公开
标题翻译：芯片芯片和包装封装技术的灵活包装
公开(公告)号：JP2010219539A
公开(公告)日：2010-09-30
申请号：JP2010083649
申请日：2010-03-12
申请人： Apple Inc , アップルインコーポレイテッド
发明人： VON KAENEL VINCENT R
IPC分类号： H01L25/065 , H01L25/07 , H01L25/18
CPC分类号： H01L25/105 , H01L22/32 , H01L23/49816 , H01L23/49838 , H01L23/50 , H01L24/05 , H01L24/16 , H01L24/24 , H01L24/48 , H01L24/82 , H01L25/0657 , H01L25/18 , H01L25/50 , H01L2224/0401 , H01L2224/13144 , H01L2224/1319 , H01L2224/16225 , H01L2224/24225 , H01L2224/32145 , H01L2224/48227 , H01L2224/82101 , H01L2225/0651 , H01L2225/06517 , H01L2225/06524 , H01L2225/06527 , H01L2225/06551 , H01L2225/06555 , H01L2225/06562 , H01L2225/06596 , H01L2225/1005 , H01L2225/1023 , H01L2225/1058 , H01L2924/00014 , H01L2924/0102 , H01L2924/01079 , H01L2924/07802 , H01L2924/14 , H01L2924/1433 , H01L2924/15173 , H01L2924/15192 , H01L2924/15311 , H01L2924/15312 , H01L2924/15313 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： PROBLEM TO BE SOLVED: To provide flexible packaging for chip-on-chip and package-on-package technologies. SOLUTION: A packaging solution for an application integrated circuit (IC) and one or more other ICs is provided. The packaging solution may support both chip-on-chip packaging of the application IC and other ICs, and package-on-package packaging of the application IC and the other ICs. The package substrate may include a first set of pads proximate to the application IC to support chip-on-chip connection to the other IGs. The pads may be connected to conductors that extend underneath the application IC, to connect to the application IC. If the chip-on-chip solution proves reliable, support for the package-on-package solution may be eliminated and the package substrate may be reduced in size. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：为片上芯片和封装封装技术提供灵活的封装。解决方案：提供了一种用于应用集成电路（IC）和一个或多个其他IC的封装解决方案。封装解决方案可以支持应用IC和其他IC的片上芯片封装以及应用IC和其他IC的封装封装封装。封装衬底可以包括靠近应用IC的第一组焊盘，以支持与其它IG的芯片上芯片连接。焊盘可以连接到延伸在应用IC下面的导体，以连接到应用IC。如果片上芯片解决方案证明是可靠的，则可以消除对封装封装解决方案的支持，并且可以减小封装衬底的尺寸。版权所有（C）2010，JPO＆INPIT

3. 发明专利

JP2013031207A Dynamic voltage and frequency management 有权
标题翻译：动态电压和频率管理
公开(公告)号：JP2013031207A
公开(公告)日：2013-02-07
申请号：JP2012200727
申请日：2012-09-12
申请人： Apple Inc , アップルインコーポレイテッド
发明人： VON KAENEL VINCENT R
IPC分类号： H03K19/00
CPC分类号： H03K19/0008 , G06F1/3203 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： PROBLEM TO BE SOLVED: To determine supply voltage magnitudes that ensure correct operation at the given frequency across all acceptable variations in the manufacturing process and all permissible operating temperatures.SOLUTION: An integrated circuit includes a self calibration unit configured to iterate a test on a logic circuit in the integrated circuit at respectively lower requested supply voltage magnitudes until the test fails. A lowest requested supply voltage magnitude at which the test passes is used to generate a requested supply voltage magnitude for the integrated circuit. The integrated circuit includes a series connection of logic gates physically distributed over an area of the integrated circuit, and a measurement unit configured to launch a logical transition into the series and detect a corresponding transition at the output of the series. The amount of time between the launch and the detection is used to request a supply voltage magnitude for the integrated circuit.
摘要翻译：要解决的问题：确定在制造过程中所有可接受的变化和所有允许的工作温度下确保在给定频率下正确工作的电源电压幅值。解决方案：集成电路包括自校准单元，其被配置为在分别较低的请求电源电压幅度下对集成电路中的逻辑电路进行测试，直到测试失败为止。测试通过的最低要求电源电压幅度用于为集成电路产生所请求的电源电压幅度。集成电路包括物理分布在集成电路的区域上的逻辑门的串联连接，以及测量单元，被配置为将逻辑转换发射到串联中并检测在该系列的输出处的相应转变。发射和检测之间的时间量用于请求集成电路的电源电压幅值。版权所有（C）2013，JPO＆INPIT

4. 发明专利

AU2010208458B2 Dynamic voltage and frequency management 未知
公开(公告)号：AU2010208458B2
公开(公告)日：2012-02-02
申请号：AU2010208458
申请日：2010-01-22
申请人： APPLE INC
发明人： VON KAENEL VINCENT R
IPC分类号： G06F1/32
摘要： In one embodiment, an integrated circuit includes a self calibration unit configured to iterate a test on a logic circuit in the integrated circuit at respectively lower supply voltage magnitudes until the test fails. A lowest supply voltage magnitude at which the test passes is used to generate a requested supply voltage magnitude for the integrated circuit. In an embodiment, an integrated circuit includes a series connection of logic gates physically distributed over an area of the integrated circuit, and a measurement unit configured to launch a logical transition into the series and detect a corresponding transition at the output of the series. The amount of time between the launch and the detection is used to request a supply voltage magnitude for the integrated circuit.

5. 发明专利

AU2011226847A1 Dynamic voltage and frequency management 未知
公开(公告)号：AU2011226847A1
公开(公告)日：2011-10-13
申请号：AU2011226847
申请日：2011-09-23
申请人： APPLE INC
发明人： VON KAENEL VINCENT R
IPC分类号： G06F1/32
摘要： A~n integrated circuit includes a logic circuit, a local power manager coupled to the logic circuit, and a self calibration unit. The local power manager is configured to transmit an indication of a requested supply voltage magnitude to an external power supply. The self calibration unit is configured to execute a test on the logic circuit, and to iterate the test at respectively lower requested supply voltage magnitudes until the test fails. A lowest requested supply voltage magnitude at which the test passes is used to generate the requested supply voltage magnitude for operation of the integrated circuit. The self calibration unit is further configured to iterate the test and determine the lowest requested supply voltage magnitude in response to the logic circuit executing a different workload.

6. 发明专利

DK1899975T3 Integreret kredsløb med adskilt forsyningsspænding til lager, som er forskelligt fra forsyningsspændingen af det logiske kredsløb 未知
公开(公告)号：DK1899975T3
公开(公告)日：2011-09-26
申请号：DK06774493
申请日：2006-06-30
申请人： APPLE INC
发明人： CAMPBELL BRIAN J , VON KAENEL VINCENT R , SCOTT GREGORY S , SANTHANAM SRIBALAN , MURRAY DANIEL C
IPC分类号： G11C5/14

7. 发明专利

HK1169222A1 DELAY LOCKED LOOP INCLUDING A MECHANISM FOR REDUCING LOCK TIME 未知
公开(公告)号：HK1169222A1
公开(公告)日：2013-01-18
申请号：HK12109708
申请日：2012-10-03
申请人： APPLE INC
发明人： TRIVEDI PRADEEP R , VON KAENEL VINCENT R
IPC分类号： H03L20060101
摘要： A delay locked loop (DLL) includes a delay line configured to provide a delayed version of a reference clock as a feedback clock. The DLL also includes a phase detector that may provide an output signal that is indicative of a change in a delay associated with the delay line. The DLL may also include a step size controller that may provide a step size indication corresponding to a first step size in response to detecting the output signal indicating a first change in delay, and to provide a step size indications corresponding to a second step size that is smaller than the first step size in response to detecting the output signal indicating a second change in delay.

8. 发明专利

HK1164531A1 DYNAMIC LEAKAGE CONTROL FOR MEMORY ARRAYS 未知
公开(公告)号：HK1164531A1
公开(公告)日：2012-09-21
申请号：HK12104747
申请日：2012-05-15
申请人： APPLE INC
发明人： SHIU SHINYE , VON KAENEL VINCENT R
IPC分类号： G11C20060101
摘要： A memory circuit is disclosed that comprises a plurality of memory cells coupled to a virtual voltage rail. The plurality of memory cells may form, for example, a sub-array of an SRAM array. A switching circuit may be coupled between the virtual voltage rail and a voltage supply node, and a comparator may be coupled to compare a voltage level present on the virtual voltage rail to a reference voltage to thereby provide an output signal based on the comparison. The switching circuit may be configured to electrically couple the virtual voltage rail to the voltage supply node depending upon the output signal. In some embodiments, the switching circuit may be implemented using either a PMOS transistor or an NMOS transistor, although other embodiments may employ other switching circuits.

9. 发明专利

AU2012204142A1 Double-sided flip chip package 未知
公开(公告)号：AU2012204142A1
公开(公告)日：2013-02-07
申请号：AU2012204142
申请日：2012-07-12
申请人： APPLE INC
发明人： ZHAI JUN , VON KAENEL VINCENT R
IPC分类号： H01L21/44
摘要： Semiconductor device modules having two or more integrated circuit dies mounted on opposing sides of a substrate. The integrated circuit dies are mounted by use of surface mount connections, such as flip chip connections implemented using conductive bumps. 5 Systems may include one or more of the present semiconductor device modules, and in some cases may also include other modules, such as a system module. 110a 22110b 200b 20a100 130 { 130 VVVV VVu .VVV VVVVVV VVVVVV VV VVVV VVV 200bor 3 100 110b 1)3 130 110a 210a 200a 210c 200c 130 110a 130 o 0 0 0 0 0 0 o 0 0 120a 120c o 0 0 0 0 0 0 0 0 0 0 0 io o o lo o o 0 o 0~l 0 o00 01 lo o o o10 o oi o l o0 0 lo o o ol lo o o ol 0 o 10 0 0 01 10 0 0 o o 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

10. 发明专利

HK1161415A1 SRAM WITH DIFFERENT SUPPLY VOLTAGES FOR MEMORY CELLS AND ACCESS LOGIC CIRCUITRY 未知
公开(公告)号：HK1161415A1
公开(公告)日：2012-08-24
申请号：HK12101530
申请日：2012-02-16
申请人： APPLE INC
发明人： CAMPBELL BRIAN J , VON KAENEL VINCENT R , SCOTT GREGORY S , SANTHANAM SRIBALAN , MURRAY DANIEL C
IPC分类号： G11C20060101

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