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1. 发明专利

JP2000010814A CHIP WITH DEBUGGING CAPABILITY 失效
公开(公告)号：JP2000010814A
公开(公告)日：2000-01-14
申请号：JP13332699
申请日：1999-05-13
申请人： AXIS AB , AXIS AB
发明人： BENGTSSON JAN , RANERUP KEENY , ZANDER PER
IPC分类号： G06F11/28
摘要： PROBLEM TO BE SOLVED: To monitor the execution of a program in real time over a wide range by making a chip include a debug bus which can be connected to another identical chip so that while a MONITOR mode and a DUT mode are set to complementary modes, signals enabling a chip and another chip to be operated in parallel are transferred. SOLUTION: When a power source is turned on, not only a debug chip 110C in a DUT mode, but also MONITOR-mode chips 110A to 110B are reset with an energized RESET signal. In this case, when the RESET signal is energized, the MONITOR-mode chips 110A to 110B reports the debug bus 140 that an enable signal is generated and the DUT-mode debug chip 110C that the debug bus of its CODEC is enabled. The 2nd synchronization unit of the debug chip 110C in the DUT mode, on the other hand, synchronizes the reset signal.

2. 发明专利

JP2000082011A IMPROVED MEMORY ACCESS METHOD USING DMA UNIT AND COMPUTER SYSTEM 失效
公开(公告)号：JP2000082011A
公开(公告)日：2000-03-21
申请号：JP17011499
申请日：1999-05-13
申请人： AXIS AB
发明人： BENGTSSON JAN , RANERUP KEENY , ZANDER PER
IPC分类号： G06F12/08 , G06F13/28
摘要： PROBLEM TO BE SOLVED: To attain an effective operation of a computer system having a cache memory and a main memory by allowing a DMA unit to access the cache memory while a processor is kept in its halted state to decide a cache hit or cache miss. SOLUTION: This computer system includes a processor, a cache system, a DMA unit 114, a memory controller 116 and a main memory 104. A memory access method includes a step where a cooperative memory operation is secured between the unit 114 and the processor and a step where the unit 114 and a cache memory are available in addition to the processor owing to the said cooperative step. Furthermore, the cooperative step includes another step as necessary to allow the unit 114 to access the cache memory while the processor is kept in its halt state and to decide a cache hit or cache miss.

3. 发明专利

JP2000059439A REMOTE BUILDUP METHOD FOR DEVICES IN NETWORK CONNECTION, METHOD FOR ALLOWING INTEGRATED CIRCUIT FOR EXECUTING INSTRUCTION, AND THE INTEGRATED CIRCUIT 失效
公开(公告)号：JP2000059439A
公开(公告)日：2000-02-25
申请号：JP17149799
申请日：1999-05-13
申请人： AXIS AB
发明人： BENGTSSON JAN , RANERUP KEENY , ZANDER PER
IPC分类号： H04L12/28 , H04L12/70 , H04L12/56
摘要： PROBLEM TO BE SOLVED: To provide an integrated circuit that is used for a wide variety of applications by allowing a CPU on the integrated circuit for executing an instruction received in terms of an external signal in the start mode, so as to simplify loading of a required software program to a processing circuit. SOLUTION: A server 102 starts a processor as a result of a program code 108 stored in a storage device 104. The processor assembles packets, having a group ID and transmits them through a network 100. Each of multi-mode chips 140A-D receives an initial packet whose destination address has the group ID. Each of the multi-mode chips 140A-D starts temporal process sets 160A-D with a temporal code sent from the server 102 by the initial packet among eh received packets. Each chip extracts the identifiers of the packets and identifies each peripheral equipment, to which each chip is attached. The multi- mode chips 140A-D send acknowledgment packets to the server 102 in response to them.

4. 发明专利

JP2000082037A APPLICATION SPECIFIC INTEGRATED CIRCUIT AND TRANSCEIVER CIRCUIT 失效
公开(公告)号：JP2000082037A
公开(公告)日：2000-03-21
申请号：JP13332799
申请日：1999-05-13
申请人： AXIS AB
发明人： BENGTSSON JAN , RANERUP KEENY
IPC分类号： G06F13/368 , G06F13/38 , G06F13/40
摘要： PROBLEM TO BE SOLVED: To obtain the application specific integrated circuit(ASIC) adaptive to the ATA or SCSI communication protocol. SOLUTION: The ASIC includes an integrated CPU 10, an integrated network interface controller(NIC) 11, I/O devices 13 to 16 including ones for ATA 16 and SCSI 15, their signal buffers, and the transceiver circuit for amplification and has totem pole output or open-drain output as its output, which can be enabled and outputted to positive NOT or wired-OR. The ATA or SCSI device has a port for external transceiver connection. A SCSI signal is buffered, amplified, and outputted as mentioned above through the unidirectional line from the ASIC.

5. 发明专利

SE9801678D0 未知
公开(公告)号：SE9801678D0
公开(公告)日：1998-05-13
申请号：SE9801678
申请日：1998-05-13
申请人： AXIS AB
发明人： BENGTSSON JAN , RANERUP KEENY , ZANDER PER
IPC分类号： G06F11/36 , G06F

6. 发明专利

SE520107C2 Providing more efficient operation of a memory shared by a central processor unit and by a direct memory access unit using a computer system 未知
公开(公告)号：SE520107C2
公开(公告)日：2003-05-27
申请号：SE9801679
申请日：1998-05-13
申请人： AXIS AB
发明人： BENGTSSON JAN , RANERUP KENNY , ZANDER PER
IPC分类号： G06F20060101 , G06F13/28
摘要： A computer system includes a central processor unit (110) and a cache memory (140), a cache controller (116), a direct memory access (DMA) unit (114) and a main memory (104). A cache controller (132) implements the appropriate cache policy for the CPU and DMA devices both for the cache memory and the main memory, while the cache controller and DMA unit control access of the DMA unit and processor to the cache memory, to reduce the number of processor operations leading to main memory access. Independent claims are included for a computer system, for a method of managing data requests and for a DMA system.

7. 发明专利

SE520102C2 未知
公开(公告)号：SE520102C2
公开(公告)日：2003-05-27
申请号：SE9801674
申请日：1998-05-13
申请人： AXIS AB
发明人： BENGTSSON JAN , RANERUP KENNY
IPC分类号： G06F13/38 , G06F13/40 , G06F13/368
摘要： The present invention relates to an application specific integrated circuit (ASIC) comprising an integrated central processor unit (CPU) (10), an integrated network interface control (NIC) (11) and at least one integrated input/output (I/O) device (13-16), and a transceiver circuit for buffering and amplifying SCSI signals from such an ASIC, whereby the outputs can be enabled to function as totem-pole or open-drain outputs, for active negation and wired-OR, respectively.According to the invention at least one I/O device is an ATA (16) or SCSI (15) device, with ports for connection to an external transceiver.The invention also relates to such a transceiver circuit for buffering and amplifying SCSI signals on single direction lines from an ASIC, whereby the outputs to the SCSI bus can be enabled to function as totem-pole or open-drain outputs, for active negation and wired-OR, respectively. In this circuit the same data transmission lines between the transceiver circuit and the ASIC is used for wired-OR and for active negation.

8. 发明专利

SE520101C2 未知
公开(公告)号：SE520101C2
公开(公告)日：2003-05-27
申请号：SE9801671
申请日：1998-05-13
申请人： AXIS AB
发明人： BENGTSSON JAN , RANERUP KENNY , ZANDER PER
IPC分类号： G06F9/445 , G06F9/44
摘要： An integrated circuit comprises a CPU, ports for external communication, a memory means and a switching means for converting the circuit between a working mode and an initiating mode. The circuit is in itself, in the initiating mode, adapted to receive an initiating signal, comprising external instructions, and to bring the CPU to execute said instructions. According to a method for bringing the integrated circuit to execute instructions, the integrated circuit is in a first step brought into the initiating mode. Thereafter the circuit receives said external signal and uses the integrated CPU to execute said instructions.

9. 发明专利

SE9901742L 未知
公开(公告)号：SE9901742L
公开(公告)日：1999-11-14
申请号：SE9901742
申请日：1999-05-11
申请人： AXIS AB
发明人： BENGTSSON JAN , RANERUP KENNY , ZANDER PER
IPC分类号： G06F20060101 , G06F11/00

10. 发明专利

SE9901742D0 未知
公开(公告)号：SE9901742D0
公开(公告)日：1999-05-11
申请号：SE9901742
申请日：1999-05-11
申请人： AXIS AB
发明人： BENGTSSON JAN , RANERUP KENNY , ZANDER PER
IPC分类号： G06F20060101 , G06F11/00 , G06F

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