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1. 发明申请

US20090175399A1 DIGITAL PHASE-LOCKED LOOP WITH GATED TIME-TO-DIGITAL CONVERTER 有权
标题翻译：数字锁相环与定位的时间到数字转换器
公开(公告)号：US20090175399A1
公开(公告)日：2009-07-09
申请号：US11969359
申请日：2008-01-04
申请人： Bo Sun , Gurkanwal Singh Sahota , Zixiang Yang
发明人： Bo Sun , Gurkanwal Singh Sahota , Zixiang Yang
IPC分类号： H03D3/24
CPC分类号： H03L7/0802 , H03L7/087
摘要： A digital PLL (DPLL) includes a time-to-digital converter (TDC) and a control unit. The TDC is periodically enabled for a short duration to quantize phase information and disabled for the remaining time to reduce power consumption. The TDC receives a first clock signal and a first reference signal and provides a TDC output indicative of the phase difference between the first clock signal and the first reference signal. The control unit generates an enable signal based on a main reference signal and enables and disables the TDC with the enable signal. In one design, the control unit delays the main reference signal to obtain the first reference signal and a second reference signal, generates the enable signal based on the main reference signal and the second reference signal, and gates a main clock signal with the enable signal to obtain the first clock signal for the TDC.
摘要翻译：数字PLL（DPLL）包括时间 - 数字转换器（TDC）和控制单元。定期启用TDC以持续短时间量化相位信息，并在剩余时间内禁用TDC以降低功耗。 TDC接收第一时钟信号和第一参考信号，并提供指示第一时钟信号和第一参考信号之间的相位差的TDC输出。控制单元基于主参考信号生成使能信号，并使能和禁止具有使能信号的TDC。在一种设计中，控制单元延迟主参考信号以获得第一参考信号和第二参考信号，基于主参考信号和第二参考信号产生使能信号，并且将主时钟信号与使能信号以获得TDC的第一个时钟信号。

2. 发明申请

US20090262878A1 SYSTEM AND METHOD OF CALIBRATING POWER-ON GATING WINDOW FOR A TIME-TO-DIGITAL CONVERTER (TDC) OF A DIGITAL PHASE LOCKED LOOP (DPLL) 有权
标题翻译：用于数字相位锁定（DPLL）的时间到数字转换器（TDC）的校准功率增益窗口的系统和方法
公开(公告)号：US20090262878A1
公开(公告)日：2009-10-22
申请号：US12107584
申请日：2008-04-22
申请人： Bo Sun , Gurkanwal Singh Sahota , Zixiang Yang
发明人： Bo Sun , Gurkanwal Singh Sahota , Zixiang Yang
IPC分类号： H04L7/00 , H03L7/06
CPC分类号： H03L7/085 , H03L7/18 , H03L2207/50
摘要： A system and method are disclosed related to calibrating a power-on gating window for a time-to-digital converter (TDC) of a digital phase locked loop (DPLL). The gating window is calibrated to ensure proper operation of the DPLL, while at the same time operating the TDC in a power efficient manner. In particular, the technique entails setting the width of the TDC gating window to a default value; operating the DPLL until the control loop is substantially locked; decreasing the width of the TDC gating window by a predetermined amount, while monitoring the phase error signal generated by the phase error device of the DPLL; determining the current width of the TDC gating window at substantially a time when the phase error arrives at or crosses a predetermined threshold; and increasing the current width of the TDC gating window by a predetermined amount to build in a margin of error for the operating width of the TDC gating window.
摘要翻译：公开了一种系统和方法，用于校准数字锁相环（DPLL）的时间 - 数字转换器（TDC）的上电门控窗口。门控窗口被校准，以确保DPLL的正常运行，同时以高效的方式操作TDC。特别地，该技术需要将TDC门控窗口的宽度设置为默认值; 操作DPLL直到控制回路基本锁定; 同时监视由DPLL的相位误差装置产生的相位误差信号，将TDC门控窗口的宽度减小预定量; 在相位误差到达或超过预定阈值的时间基本上确定TDC门控窗口的当前宽度; 并且将TDC门控窗口的当前宽度增加预定量以构成TDC门控窗口的操作宽度的误差范围。

3. 发明授权

US08433025B2 Digital phase-locked loop with gated time-to-digital converter 有权
标题翻译：带门控时钟数字转换器的数字锁相环
公开(公告)号：US08433025B2
公开(公告)日：2013-04-30
申请号：US11969359
申请日：2008-01-04
申请人： Bo Sun , Gurkanwal Singh Sahota , Zixiang Yang
发明人： Bo Sun , Gurkanwal Singh Sahota , Zixiang Yang
IPC分类号： H03D3/24
CPC分类号： H03L7/0802 , H03L7/087
摘要： A digital PLL (DPLL) includes a time-to-digital converter (TDC) and a control unit. The TDC is periodically enabled for a short duration to quantize phase information and disabled for the remaining time to reduce power consumption. The TDC receives a first clock signal and a first reference signal and provides a TDC output indicative of the phase difference between the first clock signal and the first reference signal. The control unit generates an enable signal based on a main reference signal and enables and disables the TDC with the enable signal. In one design, the control unit delays the main reference signal to obtain the first reference signal and a second reference signal, generates the enable signal based on the main reference signal and the second reference signal, and gates a main clock signal with the enable signal to obtain the first clock signal for the TDC.
摘要翻译：数字PLL（DPLL）包括时间 - 数字转换器（TDC）和控制单元。定期启用TDC以持续短时间量化相位信息，并在剩余时间内禁用TDC以降低功耗。 TDC接收第一时钟信号和第一参考信号，并提供指示第一时钟信号和第一参考信号之间的相位差的TDC输出。控制单元基于主参考信号生成使能信号，并使能和禁止具有使能信号的TDC。在一种设计中，控制单元延迟主参考信号以获得第一参考信号和第二参考信号，基于主参考信号和第二参考信号产生使能信号，并且将主时钟信号与使能信号以获得TDC的第一个时钟信号。

4. 发明授权

US08090068B2 System and method of calibrating power-on gating window for a time-to-digital converter (TDC) of a digital phase locked loop (DPLL) 有权
标题翻译：用于数字锁相环（DPLL）的时间 - 数字转换器（TDC）校准电源门控窗口的系统和方法
公开(公告)号：US08090068B2
公开(公告)日：2012-01-03
申请号：US12107584
申请日：2008-04-22
申请人： Bo Sun , Gurkanwal Singh Sahota , Zixiang Yang
发明人： Bo Sun , Gurkanwal Singh Sahota , Zixiang Yang
IPC分类号： H03D3/24
CPC分类号： H03L7/085 , H03L7/18 , H03L2207/50
摘要： A system and method are disclosed related to calibrating a power-on gating window for a time-to-digital converter (TDC) of a digital phase locked loop (DPLL). The gating window is calibrated to ensure proper operation of the DPLL, while at the same time operating the TDC in a power efficient manner. In particular, the technique entails setting the width of the TDC gating window to a default value; operating the DPLL until the control loop is substantially locked; decreasing the width of the TDC gating window by a predetermined amount, while monitoring the phase error signal generated by the phase error device of the DPLL; determining the current width of the TDC gating window at substantially a time when the phase error arrives at or crosses a predetermined threshold; and increasing the current width of the TDC gating window by a predetermined amount to build in a margin of error for the operating width of the TDC gating window.
摘要翻译：公开了一种系统和方法，用于校准数字锁相环（DPLL）的时间 - 数字转换器（TDC）的上电门控窗口。门控窗口被校准，以确保DPLL的正常运行，同时以高效的方式操作TDC。特别地，该技术需要将TDC门控窗口的宽度设置为默认值; 操作DPLL直到控制回路基本锁定; 同时监视由DPLL的相位误差装置产生的相位误差信号，将TDC门控窗口的宽度减小预定量; 在相位误差到达或超过预定阈值的时间基本上确定TDC门控窗口的当前宽度; 并且将TDC门控窗口的当前宽度增加预定量以构成TDC门控窗口的操作宽度的误差范围。

5. 发明申请

US20100102894A1 DIGITALLY CONTROLLED OSCILLATOR WITH IMPROVED DIGITAL FREQUENCY CALIBRATION 失效
标题翻译：具有改进数字频率校准的数字控制振荡器
公开(公告)号：US20100102894A1
公开(公告)日：2010-04-29
申请号：US12366576
申请日：2009-02-05
申请人： Bo Sun , Zixiang Yang
发明人： Bo Sun , Zixiang Yang
IPC分类号： H03L7/099
CPC分类号： H03L7/099 , H03B5/1265 , H03J1/0008 , H03J2200/10 , H03L7/10 , H03L2207/06 , H03L2207/50 , H03M1/1019 , H03M1/1042 , H03M1/1047 , H03M1/682 , H03M1/86
摘要： Techniques for calibrating digitally controlled oscillators (DCOS) are disclosed. In one aspect of the disclosure, an initial set of control codes for operating the DCO with a coarse frequency tuning bank with multiple overlapping coarse frequency tuning segments (LTBs) and one fine main frequency tuning bank (MTB) is determined. A range of output frequencies produced from the initial set is identified. Instances of overlap are identified in the frequency range between consecutive LTB segments. An offset in the MTB is added that corresponds to the overlap instance between consecutive LTBs to establish a revised set. The revised control codes are utilized to tune the DCO over the desired frequency range.
摘要翻译：公开了用于校准数字控制振荡器（DCOS）的技术。在本公开的一个方面，确定用于利用具有多个重叠粗调频调谐段（LTB）和一个精细主频调谐组（MTB）的粗调频调谐组操作DCO的初始控制码组。识别从初始集合产生的输出频率范围。在连续的LTB段之间的频率范围内识别重叠实例。添加MTB中的偏移量，其对应于连续LTB之间的重叠实例，以建立修订集。修改后的控制代码用于在期望的频率范围内调谐DCO。

6. 发明申请

US20090219073A1 HIGH RESOLUTION TIME-TO-DIGITAL CONVERTER 有权
标题翻译：高分辨率时间到数字转换器
公开(公告)号：US20090219073A1
公开(公告)日：2009-09-03
申请号：US12041426
申请日：2008-03-03
申请人： Bo Sun , Zixiang Yang
发明人： Bo Sun , Zixiang Yang
IPC分类号： H03H11/26
CPC分类号： G04F10/005
摘要： A time-to-digital converter (TDC) can have a resolution that is finer than the propagation delay of an inverter. In one example, a fractional-delay element circuit receives a TDC input signal and generates therefrom a second signal that is a time-shifted facsimile of a first signal. The first signal is supplied to a first delay line timestamp circuit (DLTC) and the second signal is supplied to a second DLTC. The first DLTC generates a first timestamp indicative of a time between an edge of a reference input signal to the TDC and an edge of the first signal. The second DLTC generates a second timestamp indicative of a time between the edge of the reference input signal and an edge of the second signal. The first and second timestamps are combined and together constitute a high-resolution overall TDC timestamp that has a finer resolution than either the first or second timestamps.
摘要翻译：时间 - 数字转换器（TDC）可以具有比逆变器的传播延迟更精细的分辨率。在一个示例中，分数延迟元件电路接收TDC输入信号并由此产生作为第一信号的时移传真的第二信号。第一信号被提供给第一延迟线时间戳电路（DLTC），第二信号被提供给第二DLTC。第一DLTC产生指示参考输入信号与TDC的边缘和第一信号的边缘之间的时间的第一时间戳。第二DLTC产生指示参考输入信号的边缘与第二信号的边缘之间的时间的第二时间戳。组合第一和第二时间戳并且一起构成具有比第一或第二时间戳更精细的分辨率的高分辨率整体TDC时间戳。

7. 发明授权

US07911269B2 Ultra low noise high linearity LNA for multi-mode transceiver 有权
标题翻译：用于多模收发器的超低噪声高线性度LNA
公开(公告)号：US07911269B2
公开(公告)日：2011-03-22
申请号：US12355860
申请日：2009-01-19
申请人： Zixiang Yang , Chiewcharn Narathong , Bo Sun
发明人： Zixiang Yang , Chiewcharn Narathong , Bo Sun
IPC分类号： H03F1/14
CPC分类号： H03F3/193 , H03F1/3205 , H03F1/3211 , H03F3/45183 , H03F3/72 , H03F2200/294 , H03F2200/451 , H03F2203/45386 , H03F2203/45481 , H03F2203/7221
摘要： An amplifier for operating at low, middle or high linearity modes, the amplifier comprising a first low noise amplifier (LNA) coupled to a second low noise amplifier for providing amplification; a first degeneration inductor coupled to the first LNA for providing impedance matching; a −g3 generation block coupled to an output of the second LNA for canceling third-order transconductance distortion; and a first enabling/disabling component coupled to the output of the second LNA and aligned in parallel with the −g3 generation block for operating at least one of the first and second LNAs at one of the low, middle or high linearity modes.
摘要翻译：一种用于在低，中或高线性模式下操作的放大器，所述放大器包括耦合到第二低噪声放大器以提供放大的第一低噪声放大器（LNA）耦合到第一LNA的第一退化电感器，用于提供阻抗匹配; 耦合到所述第二LNA的输出以消除三阶跨导失真的-g3生成块; 以及耦合到第二LNA的输出并且与-g3生成块并行对准的第一使能/禁用组件，用于在低，中或高线性模式中的一个模式下操作第一和第二LNA中的至少一个。

8. 发明申请

US20090219187A1 HIGH-SPEED TIME-TO-DIGITAL CONVERTER 有权
标题翻译：高速时数转换器
公开(公告)号：US20090219187A1
公开(公告)日：2009-09-03
申请号：US12041403
申请日：2008-03-03
申请人： Bo Sun , Zixiang Yang
发明人： Bo Sun , Zixiang Yang
IPC分类号： H03M1/50
CPC分类号： G04F10/005
摘要： Techniques for enabling a time-to-digital (TDC) to sample with sub-inverter delay resolution are disclosed. In an embodiment, the inputs to a differential D-Q flip-flop in the TDC are coupled to a single-ended signal and a delayed and inverted version of that signal to allow time interpolation of the signal. Further disclosed are techniques to balance the loads of a first delay line and a complementary delay line within the TDC.
摘要翻译：公开了一种能够实现时间数字（TDC）采用次逆变器延迟分辨率的技术。在一个实施例中，TDC中的差分D-Q触发器的输入被耦合到单端信号和该信号的延迟和反相版本，以允许信号的时间插值。进一步公开的是平衡TDC内的第一延迟线和互补延迟线的负载的技术。

9. 发明授权

US07808418B2 High-speed time-to-digital converter 有权
标题翻译：高速时数转换器
公开(公告)号：US07808418B2
公开(公告)日：2010-10-05
申请号：US12041403
申请日：2008-03-03
申请人： Bo Sun , Zixiang Yang
发明人： Bo Sun , Zixiang Yang
IPC分类号： H03M1/50
CPC分类号： G04F10/005
摘要： Techniques for enabling a time-to-digital (TDC) to sample with sub-inverter delay resolution are disclosed. In an embodiment, the inputs to a differential D-Q flip-flop in the TDC are coupled to a single-ended signal and a delayed and inverted version of that signal to allow time interpolation of the signal. Further disclosed are techniques to balance the loads of a first delay line and a complementary delay line within the TDC.
摘要翻译：公开了一种能够实现时间数字（TDC）采用次逆变器延迟分辨率的技术。在一个实施例中，TDC中的差分D-Q触发器的输入被耦合到单端信号和该信号的延迟和反相版本，以允许信号的时间插值。进一步公开的是平衡TDC内的第一延迟线和互补延迟线的负载的技术。

10. 发明申请

US20100182090A1 ULTRA LOW NOISE HIGH LINEARITY LNA FOR MULTI-MODE TRANSCEIVER 有权
标题翻译：用于多模式收发器的超低噪声高线性度LNA
公开(公告)号：US20100182090A1
公开(公告)日：2010-07-22
申请号：US12355860
申请日：2009-01-19
申请人： Zixiang Yang , Chiewcharn Narathong , Bo Sun
发明人： Zixiang Yang , Chiewcharn Narathong , Bo Sun
IPC分类号： H03F3/16
CPC分类号： H03F3/193 , H03F1/3205 , H03F1/3211 , H03F3/45183 , H03F3/72 , H03F2200/294 , H03F2200/451 , H03F2203/45386 , H03F2203/45481 , H03F2203/7221
摘要： An amplifier for operating at low, middle or high linearity modes, the amplifier comprising a first low noise amplifier (LNA) coupled to a second low noise amplifier for providing amplification; a first degeneration inductor coupled to the first LNA for providing impedance matching; a −g3 generation block coupled to an output of the second LNA for canceling third-order transconductance distortion; and a first enabling/disabling component coupled to the output of the second LNA and aligned in parallel with the −g3 generation block for operating at least one of the first and second LNAs at one of the low, middle or high linearity modes.
摘要翻译：一种用于在低，中或高线性模式下操作的放大器，所述放大器包括耦合到第二低噪声放大器以提供放大的第一低噪声放大器（LNA）耦合到第一LNA的第一退化电感器，用于提供阻抗匹配; 耦合到所述第二LNA的输出以消除三阶跨导失真的-g3生成块; 以及耦合到第二LNA的输出并且与-g3生成块并行对准的第一使能/禁用组件，用于在低，中或高线性模式中的一个模式下操作第一和第二LNA中的至少一个。

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