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1. 发明申请

US20060073642A1 Method for manufacturing a multiple-bit-per-cell memory 有权
公开(公告)号：US20060073642A1
公开(公告)日：2006-04-06
申请号：US11285614
申请日：2005-11-21
申请人： Chih Yeh , Han Lai , Wen Tsai , Tao Lu , Chih Lu
发明人： Chih Yeh , Han Lai , Wen Tsai , Tao Lu , Chih Lu
IPC分类号： H01L21/82 , H01L21/326 , H01L21/44
CPC分类号： G11C11/5692 , H01L27/101
摘要： A method for manufacturing an electrically programmable non-volatile memory cell comprises forming a first electrode on a substrate, forming an inter-electrode layer of material on the first electrode having a property which is characterized by progressive change in response to stress, and forming a second electrode over the inter-electrode layer of material. The inter-electrode layer comprises a dielectric layer, such as ultra-thin oxide, between the first and second electrodes. A programmable resistance, or other property, is established by stressing the dielectric layer, representing stored data. Embodiments of the memory cell are adapted to store multiple bits of data per cell and/or adapted for programming more than one time without an erase process.

2. 发明申请

US20050037546A1 Method for manufacturing a programmable eraseless memory 有权
标题翻译：制造可编程擦除存储器的方法
公开(公告)号：US20050037546A1
公开(公告)日：2005-02-17
申请号：US10641897
申请日：2003-08-15
申请人： Chih Yeh , Han Lai , Wen Tsai , Tao Lu , Chih Lu
发明人： Chih Yeh , Han Lai , Wen Tsai , Tao Lu , Chih Lu
IPC分类号： G11C11/56 , H01L27/10 , H01L21/44 , H01L21/82
CPC分类号： G11C11/5692 , H01L27/101
摘要： A method for manufacturing an electrically programmable non-volatile memory cell comprises forming a first electrode on a substrate, forming an inter-electrode layer of material on the first electrode having a property which is characterized by progressive change in response to stress, and forming a second electrode over the inter-electrode layer of material. The inter-electrode layer comprises a dielectric layer, such as ultra-thin oxide, between the first and second electrodes. A programmable resistance, or other property, is established by stressing the dielectric layer, representing stored data. Embodiments of the memory cell are adapted to store multiple bits of data per cell and/or adapted for programming more than one time without an erase process.
摘要翻译：一种用于制造电可编程非易失性存储单元的方法包括在衬底上形成第一电极，在第一电极上形成具有特征在于应力的响应逐渐变化的特性的材料的电极间层，并形成第二电极在材料的电极间层之上。电极间层包括在第一和第二电极之间的介电层，例如超薄氧化物。可编程电阻或其他属性通过强调介电层来表示存储的数据来建立。存储器单元的实施例适于存储每个单元的多个数据位和/或适于在不进行擦除处理的情况下编程多于一次。

3. 发明申请

US20050190601A1 Programmable resistor eraseless memory 审中-公开
标题翻译：可编程电阻器的无刷内存
公开(公告)号：US20050190601A1
公开(公告)日：2005-09-01
申请号：US11118309
申请日：2005-04-29
申请人： Chih Yeh , Han Lai , Wen Tsai , Tao Lu , Chih Lu
发明人： Chih Yeh , Han Lai , Wen Tsai , Tao Lu , Chih Lu
IPC分类号： G11C16/04 , G11C11/56 , H01L27/10
CPC分类号： G11C11/5692
摘要： An electrically programmable non-volatile memory cell comprises a first electrode, a second electrode and an inter-electrode layer, such as ultra-thin oxide, between the first and second electrodes which is characterized by progressive change in resistance in response to program stress of relatively low voltages. A programmable resistance representing stored data is established by stressing the inter-electrode layer between the electrodes. Embodiments of the memory cell are adapted to store multiple bits of data per cell and/or adapted for programming more than one time without an erase process.
摘要翻译：电可编程非易失性存储单元包括在第一和第二电极之间的第一电极，第二电极和诸如超薄氧化物之间的电极间层，其特征在于响应于程序应力的电阻逐渐变化电压相对较低通过施加电极之间的电极间层，建立表示存储数据的可编程电阻。存储器单元的实施例适于存储每个单元的多个数据位和/或适于在不进行擦除处理的情况下编程多于一次。

4. 发明申请

US20050036368A1 Method for programming programmable eraseless memory 有权
标题翻译：编程可编程擦除存储器的方法
公开(公告)号：US20050036368A1
公开(公告)日：2005-02-17
申请号：US10642249
申请日：2003-08-15
申请人： Chih Yeh , Han Lai , Wen Tsai , Tao Lu , Chih Lu
发明人： Chih Yeh , Han Lai , Wen Tsai , Tao Lu , Chih Lu
IPC分类号： G11C13/00 , G11C11/56 , G11C17/14 , H01L27/10 , G11C11/34
CPC分类号： G11C11/5692 , G11C17/14 , G11C2211/5634 , H01L23/5252 , H01L27/101 , H01L2924/0002 , H01L2924/00
摘要： A method for programming a memory cell is based on applying stress to a memory cell, comprising a first electrode, a second electrode and an inter-electrode layer, to induce a progressive change in a property of the inter-electrode layer. The method includes a verify step including generating a signal, such as a cell current, indicating the value of the property in the selected memory cell. Then, the signal is compared with a reference signal to verify programming of the desired data. Because of the progressive nature of the change, many levels of programming can be achieved. The many levels of programming can be applied for programming a single cell more than once, without an erase process, to programming multiple bits in a single cell, and to a combination of multiple bit and multiple time of programming.
摘要翻译：用于对存储单元进行编程的方法是基于向包括第一电极，第二电极和电极间层的存储单元施加应力，以引起电极间层的性能的逐渐变化。该方法包括验证步骤，包括生成指示所选择的存储单元中的属性的值的诸如单元电流的信号。然后，将信号与参考信号进行比较，以验证所需数据的编程。由于变革的渐进性，可以实现多层次的编程。多个编程级别可以应用于单个单元的编程，而不需要擦除处理，以编程单个单元中的多个位，以及多个位和多个编程时间的组合。

5. 发明申请

US20050035429A1 Programmable eraseless memory 审中-公开
标题翻译：可编程的无刷内存
公开(公告)号：US20050035429A1
公开(公告)日：2005-02-17
申请号：US10641846
申请日：2003-08-15
申请人： Chih Yeh , Han Lai , Wen Tsai , Tao Lu , Chih Lu
发明人： Chih Yeh , Han Lai , Wen Tsai , Tao Lu , Chih Lu
IPC分类号： G11C16/04 , G11C11/56 , H01L27/10 , H01L47/00
CPC分类号： G11C11/5692
摘要： An electrically programmable non-volatile memory cell comprises a first electrode, a second electrode and an inter-electrode layer, such as ultra-thin oxide, between the first and second electrodes which is characterized by progressive change in resistance in response to program stress of relatively low voltages. A programmable resistance representing stored data is established by stressing the inter-electrode layer between the electrodes. Embodiments of the memory cell are adapted to store multiple bits of data per cell and/or adapted for programming more than one time without an erase process.
摘要翻译：电可编程非易失性存储单元包括在第一和第二电极之间的第一电极，第二电极和诸如超薄氧化物之间的电极间层，其特征在于响应于程序应力的电阻逐渐变化电压相对较低通过施加电极之间的电极间层，建立表示存储数据的可编程电阻。存储器单元的实施例适于存储每个单元的多个数据位和/或适于在不进行擦除处理的情况下编程多于一次。

6. 发明申请

US20070103991A1 INTEGRATED CODE AND DATA FLASH MEMORY 有权
标题翻译：集成代码和数据闪存
公开(公告)号：US20070103991A1
公开(公告)日：2007-05-10
申请号：US11617613
申请日：2006-12-28
申请人： Chih Yeh , Wen Tsai , Tao Lu , Chih Lu
发明人： Chih Yeh , Wen Tsai , Tao Lu , Chih Lu
IPC分类号： G11C16/04
CPC分类号： G11C16/0475 , G11C16/10 , G11C16/16
摘要： A memory architecture for an integrated circuit comprises a first memory array configured to store data for one pattern of data usage and a second memory array configured to store data for another pattern of data usage. The first and second memory arrays comprise charge storage based nonvolatile memory cells having substantially the same structure in both arrays. A first operation algorithm adapted for example for data flash applications is used for programming, erasing and reading data in the first memory array. A second operation algorithm adapted for example for code flash applications is used for programming, erasing and reading data in the second memory array, wherein the second operation algorithm is different than the first operation algorithm. Thus, one die with memory for both code flash and data flash applications can be easily manufactured using a simple process, at low cost and high yield.
摘要翻译：用于集成电路的存储器架构包括被配置为存储用于一种数据使用模式的数据的第一存储器阵列和被配置为存储用于另一数据使用模式的数据的第二存储器阵列。第一和第二存储器阵列包括在两个阵列中具有基本上相同结构的基于电荷存储的非易失性存储器单元。适用于例如数据闪存应用的第一操作算法用于在第一存储器阵列中编程，擦除和读取数据。适用于例如代码闪存应用的第二操作算法用于在第二存储器阵列中编程，擦除和读取数据，其中第二操作算法与第一操作算法不同。因此，具有用于代码闪存和数据闪存应用的存储器的一个管芯可以使用简单的工艺以低成本和高产率容易地制造。

7. 发明申请

US20050226054A1 INTEGRATED CODE AND DATA FLASH MEMORY 有权
标题翻译：集成代码和数据闪存
公开(公告)号：US20050226054A1
公开(公告)日：2005-10-13
申请号：US10815370
申请日：2004-04-01
申请人： Chih Yeh , Wen Tsai , Tao Lu , Chih Lu
发明人： Chih Yeh , Wen Tsai , Tao Lu , Chih Lu
IPC分类号： H01L27/10 , G11C11/56 , G11C16/04 , G11C16/10 , G11C16/16 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , G11C11/34
CPC分类号： G11C16/0475 , G11C16/10 , G11C16/16
摘要： A memory architecture for an integrated circuit comprises a first memory array configured to store data for one pattern of data usage and a second memory array configured to store data for another pattern of data usage. The first and second memory arrays comprise charge storage based nonvolatile memory cells having substantially the same structure in both arrays. A first operation algorithm adapted for example for data flash applications is used for programming, erasing and reading data in the first memory array. A second operation algorithm adapted for example for code flash applications is used for programming, erasing and reading data in the second memory array, wherein the second operation algorithm is different than the first operation algorithm. Thus, one die with memory for both code flash and data flash applications can be easily manufactured using a simple process, at low cost and high yield.
摘要翻译：用于集成电路的存储器架构包括被配置为存储用于一种数据使用模式的数据的第一存储器阵列和被配置为存储用于另一数据使用模式的数据的第二存储器阵列。第一和第二存储器阵列包括在两个阵列中具有基本上相同结构的基于电荷存储的非易失性存储器单元。适用于例如数据闪存应用的第一操作算法用于在第一存储器阵列中编程，擦除和读取数据。适用于例如代码闪存应用的第二操作算法用于在第二存储器阵列中编程，擦除和读取数据，其中第二操作算法与第一操作算法不同。因此，具有用于代码闪存和数据闪存应用的存储器的一个管芯可以使用简单的工艺以低成本和高产率容易地制造。

8. 发明申请

US20060050556A1 Method and apparatus for operating charge trapping nonvolatile memory 有权
标题翻译：用于操作电荷捕获非易失性存储器的方法和装置
公开(公告)号：US20060050556A1
公开(公告)日：2006-03-09
申请号：US11191367
申请日：2005-07-28
申请人： Chih Yeh , Wen Tsai , Tao Lu
发明人： Chih Yeh , Wen Tsai , Tao Lu
IPC分类号： G11C16/04
CPC分类号： G11C16/0475 , G11C16/0483 , G11C16/26
摘要： A memory cell with a charge trapping structure is operated by measuring current between the substrate region of the memory cell and at least one of the source region of the memory cell and the drain region of the memory cell. The read operation decreases the coupling between different parts of the charge trapping structure when other parts of the charge trapping structure store data that are not of interest. The sensing window of the memory cell can be greatly improved by this read operation. The memory cell is erased by increasing the net positive charge on the memory cell and programmed by increasing the net negative charge on the memory cell.
摘要翻译：具有电荷捕获结构的存储单元通过测量存储单元的衬底区域与存储单元的源极区域和存储器单元的漏极区域中的至少一个之间的电流来操作。当电荷捕获结构的其他部分存储不感兴趣的数据时，读取操作减小电荷俘获结构的不同部分之间的耦合。通过该读取操作可以极大地改善存储单元的感测窗口。通过增加存储单元上的净正电荷来擦除存储单元，并通过增加存储单元上的净负电荷进行编程。

9. 发明申请

US20050276105A1 NAND-TYPE NON-VOLATILE MEMORY CELL AND METHOD FOR OPERATING SAME 有权
标题翻译： NAND型非易失性存储器单元及其操作方法
公开(公告)号：US20050276105A1
公开(公告)日：2005-12-15
申请号：US10855286
申请日：2004-05-26
申请人： Chih Yeh , Wen Tsai , Tao Lu
发明人： Chih Yeh , Wen Tsai , Tao Lu
IPC分类号： G11C11/34 , G11C16/04 , G11C16/10 , H01L27/115
CPC分类号： G11C16/0475 , G11C16/10 , H01L27/115
摘要： A NAND-type erasable programmable read only memory (EEPROM) device formed of a number of substantially identical EEPROM cells with each EEPROM cell being capable of storing two bits of information. A simple method for operating the memory comprises erasing, programming, and reading the device.
摘要翻译：由多个基本相同的EEPROM单元形成的NAND型可擦除可编程只读存储器（EEPROM）器件，每个EEPROM单元能够存储两位信息。用于操作存储器的简单方法包括擦除，编程和读取设备。

10. 发明申请

US20060050565A1 Method and apparatus for operating nonvolatile memory in a parallel arrangement 有权
标题翻译：以并联方式操作非易失性存储器的方法和装置
公开(公告)号：US20060050565A1
公开(公告)日：2006-03-09
申请号：US11191329
申请日：2005-07-28
申请人： Chih Yeh , Wen Tsai , Tao Lu
发明人： Chih Yeh , Wen Tsai , Tao Lu
IPC分类号： G11C16/04
CPC分类号： G11C16/0475
摘要： A memory cell with a charge storage structure is read by measuring current between the substrate region of the memory cell and one of the current carrying nodes of the memory cell. The read operation decreases the coupling between different parts of the charge storage structure when other parts of the charge storage structure store data that are not of interest. The sensing window of the memory cell can be greatly improved by this read operation. Example arrangements are a single memory cell, a column or NOR-connected memory cells, and a virtual ground array of memory cells.
摘要翻译：具有电荷存储结构的存储单元通过测量存储单元的衬底区域和存储单元的一个载流节点之间的电流来读取。当电荷存储结构的其他部分存储不感兴趣的数据时，读取操作减小了电荷存储结构的不同部分之间的耦合。通过该读取操作可以极大地改善存储单元的感测窗口。示例性布置是单个存储器单元，列或NOR连接的存储器单元，以及存储器单元的虚拟接地阵列。

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