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1. 发明授权

US08786815B2 Driving circuit and display panel having the same 有权
标题翻译：驱动电路和显示面板相同
公开(公告)号：US08786815B2
公开(公告)日：2014-07-22
申请号：US13330627
申请日：2011-12-19
申请人： Chih-Hung Lin , Wu-Liu Tsai , Chuan-Sheng Wei , Che-Chia Chang , Sheng-Chao Liu , Yu-Cheng Chen , Yi-Hui Li , Maw-Song Chen
发明人： Chih-Hung Lin , Wu-Liu Tsai , Chuan-Sheng Wei , Che-Chia Chang , Sheng-Chao Liu , Yu-Cheng Chen , Yi-Hui Li , Maw-Song Chen
IPC分类号： G02F1/133 , G02F1/1368
CPC分类号： G02F1/133707 , G02F1/136213 , G02F2201/40
摘要： A display panel having a display region and a non-display region is provided. The display panel includes a plurality of pixel structures in the display region, and each pixel structure includes a scan line, a data line, a first active device, a pixel electrode, a first insulating layer, a capacitor electrode, and a second insulating layer. The first active device includes a first gate, a first channel, a first source, and a first drain. The second insulating layer covers the first insulating layer and the capacitor electrode and is located between the capacitor electrode and the first drain. At least one driving circuit is disposed in the non-display region and includes at least one second active device. Hence, a relatively thin insulating layer can be disposed between the capacitor electrode and the drain to reduce the area of the capacitor region and to achieve a desired aperture ratio.
摘要翻译：提供具有显示区域和非显示区域的显示面板。显示面板包括显示区域中的多个像素结构，并且每个像素结构包括扫描线，数据线，第一有源器件，像素电极，第一绝缘层，电容器电极和第二绝缘层。第一有源器件包括第一栅极，第一沟道，第一源极和第一漏极。第二绝缘层覆盖第一绝缘层和电容器电极，并且位于电容器电极和第一漏极之间。至少一个驱动电路设置在非显示区域中并且包括至少一个第二有源器件。因此，可以在电容器电极和漏极之间设置相对薄的绝缘层，以减小电容器区域的面积并实现所需的孔径比。

2. 发明申请

US20120092240A1 DRIVING CIRCUIT AND DISPLAY PANEL HAVING THE SAME 有权
标题翻译：驱动电路和显示面板
公开(公告)号：US20120092240A1
公开(公告)日：2012-04-19
申请号：US13330627
申请日：2011-12-19
申请人： Chih-Hung Lin , Wu-Liu Tsai , Chuan-Sheng Wei , Che-Chia Chang , Sheng-Chao Liu , Yu-Cheng Chen , Yi-Hui Li , Maw-Song Chen
发明人： Chih-Hung Lin , Wu-Liu Tsai , Chuan-Sheng Wei , Che-Chia Chang , Sheng-Chao Liu , Yu-Cheng Chen , Yi-Hui Li , Maw-Song Chen
IPC分类号： G09G3/36 , H03B1/00
CPC分类号： G02F1/133707 , G02F1/136213 , G02F2201/40
摘要： An active device, a pixel structure, and a display panel are provided. The pixel structure includes a scan line, a data line, an active device, a first insulating layer, a pixel electrode, a capacitor electrode, and a second insulating layer. The active device includes a gate, a channel, a source, and a drain. The gate is electrically connected to the scan line. The source is electrically connected to the data line. The first insulating layer is disposed between the gate and the channel. The pixel electrode is electrically connected to the drain. The capacitor electrode is located on the first insulating layer. The second insulating layer is located between the capacitor electrode and the drain.
摘要翻译：提供有源器件，像素结构和显示面板。像素结构包括扫描线，数据线，有源器件，第一绝缘层，像素电极，电容器电极和第二绝缘层。有源器件包括栅极，沟道，源极和漏极。栅极电连接到扫描线。源电连接到数据线。第一绝缘层设置在栅极和沟道之间。像素电极电连接到漏极。电容电极位于第一绝缘层上。第二绝缘层位于电容器电极和漏极之间。

3. 发明申请

US20130075766A1 THIN FILM TRANSISTOR DEVICE AND PIXEL STRUCTURE AND DRIVING CIRCUIT OF A DISPLAY PANEL 审中-公开
标题翻译：显示面板的薄膜晶体管器件和像素结构与驱动电路
公开(公告)号：US20130075766A1
公开(公告)日：2013-03-28
申请号：US13448359
申请日：2012-04-16
申请人： Che-Chia Chang , Sheng-Chao Liu , Wu-Liu Tsai , Chuan-Sheng Wei , Chih-Hung Lin
发明人： Che-Chia Chang , Sheng-Chao Liu , Wu-Liu Tsai , Chuan-Sheng Wei , Chih-Hung Lin
IPC分类号： H01L27/15 , H01L27/105
CPC分类号： G02F1/136213 , G02F1/136286 , G09G3/3677 , G09G2310/0286 , H01L27/1255
摘要： A thin film transistor device, disposed on a substrate, includes a gate electrode, a semiconductor channel layer, a gate insulating layer disposed between the gate electrode and the semiconductor channel layer, a source electrode and a drain electrode disposed at two opposite sides of the semiconductor channel layer and partially overlapping the semiconductor channel layer, respectively, a capacitor electrode at least partially overlapping the gate electrode, and a capacitor dielectric layer disposed between the capacitor electrode and the gate electrode. The capacitor electrode, the gate electrode and the capacitor dielectric layer form a capacitor device.
摘要翻译：设置在基板上的薄膜晶体管器件包括栅电极，半导体沟道层，设置在栅电极和半导体沟道层之间的栅极绝缘层，设置在栅极电极和半导体沟道层的两相对侧的源电极和漏电极半导体沟道层和半导体沟道层的部分重叠，至少部分地与栅电极重叠的电容器电极和设置在电容器电极和栅电极之间的电容器电介质层。电容器电极，栅极电极和电容器介电层形成电容器器件。

4. 发明授权

US08154061B2 Bottom gate thin film transistor and active array substrate 有权
标题翻译：底栅薄膜晶体管和有源阵列衬底
公开(公告)号：US08154061B2
公开(公告)日：2012-04-10
申请号：US12500609
申请日：2009-07-10
申请人： Chuan-Sheng Wei , Guang-Ren Shen , Chang-Yu Huang , Pei-Ming Chen , Sheng-Chao Liu , Chun-Hsiun Chen , Wei-Ming Huang
发明人： Chuan-Sheng Wei , Guang-Ren Shen , Chang-Yu Huang , Pei-Ming Chen , Sheng-Chao Liu , Chun-Hsiun Chen , Wei-Ming Huang
IPC分类号： H01L31/062
CPC分类号： H01L29/42384 , H01L29/41733 , H01L29/66765
摘要： A bottom gate thin film transistor and an active array substrate are provided. The bottom gate thin film transistor includes a gate, a gate insulation layer, a semiconductor layer, a plurality of sources and a plurality of drains. The gate insulation layer is disposed on the gate. The semiconductor layer is disposed on the gate insulation layer and located above the gate. An area ratio of the semiconductor layer and the gate is about 0.001 to 0.9. The sources are electrically connected with each other, and the drains are electrically connected with each other.
摘要翻译：提供底栅薄膜晶体管和有源阵列基板。底栅薄膜晶体管包括栅极，栅极绝缘层，半导体层，多个源极和多个漏极。栅极绝缘层设置在栅极上。半导体层设置在栅极绝缘层上并位于栅极上方。半导体层和栅极的面积比约为0.001〜0.9。源极彼此电连接，并且漏极彼此电连接。

5. 发明授权

US09030399B2 Gate driver stage outputting multiple, partially overlapping gate-line signals to a liquid crystal display 有权
标题翻译：栅极驱动器级将多个部分重叠的栅极线信号输出到液晶显示器
公开(公告)号：US09030399B2
公开(公告)日：2015-05-12
申请号：US13403434
申请日：2012-02-23
申请人： Chien-Chang Tseng , Kuang-Hsiang Liu , Sheng-Chao Liu , Che-Chia Chang , Ling-Ying Chien
发明人： Chien-Chang Tseng , Kuang-Hsiang Liu , Sheng-Chao Liu , Che-Chia Chang , Ling-Ying Chien
IPC分类号： G09G3/36 , G09G3/20
CPC分类号： G09G3/20 , G09G3/3677 , G09G2310/0218 , G09G2310/0286
摘要： A gate driver for driving a TFT-LCD panel includes a number of gate-driver circuits arranged in groups and stages. Each gate-driver circuit has a main driver and an output section. The main driver is used to provide a charging signal to the output section which has two or more output circuits. Each of the output circuits is configured to provide a gate-line signal in response to the charging signal and a clock signal. The gate-driver circuit uses fewer switching elements, such as thin-film transistors, than the conventional circuit. When the gate driver is integrated in a TFT-LCD display panel and disposed within the periphery area around the display area, it is desirable to reduce or minimize the number of switching elements in the gate driver so that the periphery area can be reduced.
摘要翻译：用于驱动TFT-LCD面板的栅极驱动器包括以组和阶段布置的多个栅极驱动器电路。每个栅极驱动器电路具有主驱动器和输出部分。主驱动器用于向具有两个或更多个输出电路的输出部分提供充电信号。每个输出电路被配置为响应于充电信号和时钟信号提供栅极线信号。栅极驱动器电路比常规电路使用更少的开关元件，例如薄膜晶体管。当栅极驱动器集成在TFT-LCD显示面板中并且设置在显示区域周围的周边区域中时，期望减小或最小化栅极驱动器中的开关元件的数量，使得可以减小外围区域。

6. 发明申请

US20100270551A1 BOTTOM GATE THIN FILM TRANSISTOR AND ACTIVE ARRAY SUBSTRATE 有权
标题翻译：底部薄膜薄膜晶体管和主动阵列基板
公开(公告)号：US20100270551A1
公开(公告)日：2010-10-28
申请号：US12500609
申请日：2009-07-10
申请人： Chuan-Sheng Wei , Guang-Ren Shen , Chang-Yu Huang , Pei-Ming Chen , Sheng-Chao Liu , Chun-Hsiun Chen , Wei-Ming Huang
发明人： Chuan-Sheng Wei , Guang-Ren Shen , Chang-Yu Huang , Pei-Ming Chen , Sheng-Chao Liu , Chun-Hsiun Chen , Wei-Ming Huang
IPC分类号： H01L33/00 , H01L29/786
CPC分类号： H01L29/42384 , H01L29/41733 , H01L29/66765
摘要： A bottom gate thin film transistor and an active array substrate are provided. The bottom gate thin film transistor includes a gate, a gate insulation layer, a semiconductor layer, a plurality of sources and a plurality of drains. The gate insulation layer is disposed on the gate. The semiconductor layer is disposed on the gate insulation layer and located above the gate. An area ratio of the semiconductor layer and the gate is about 0.001 to 0.9. The sources are electrically connected with each other, and the drains are electrically connected with each other.
摘要翻译：提供底栅薄膜晶体管和有源阵列基板。底栅薄膜晶体管包括栅极，栅极绝缘层，半导体层，多个源极和多个漏极。栅极绝缘层设置在栅极上。半导体层设置在栅极绝缘层上并位于栅极上方。半导体层和栅极的面积比约为0.001〜0.9。源极彼此电连接，并且漏极彼此电连接。

7. 发明授权

US08259895B2 Bidirectional shifter register and method of driving same 有权
标题翻译：双向移位寄存器及其驱动方法
公开(公告)号：US08259895B2
公开(公告)日：2012-09-04
申请号：US13330489
申请日：2011-12-19
申请人： Sheng-Chao Liu , Kuang-Hsiang Liu , Chien-Chang Tseng , Tsang-Hong Wang
发明人： Sheng-Chao Liu , Kuang-Hsiang Liu , Chien-Chang Tseng , Tsang-Hong Wang
IPC分类号： G11C19/00
CPC分类号： G11C19/28
摘要： A bidirectional shift register includes first, second, third and fourth control signal bus lines for providing first, second, third and fourth control signals, Bi1, Bi2, Bi3 and Bi4, respectively, and a plurality of shift register stages electrically coupled in serial, each shift register stage having first and second input nodes, where the shift register stages are grouped into a first section and a second section, where the first and second input nodes of each shift register stage in the first section are electrically coupled to the first and second control signal bus lines for receiving the first and second control signals Bi1 and Bi2, respectively, and the first and second input nodes of each shift register stage in the second section are electrically coupled to the third and fourth control signal bus lines for receiving the third and fourth control signals Bi3 and Bi4, respectively.
摘要翻译：双向移位寄存器包括用于分别提供第一，第二，第三和第四控制信号Bi1，Bi2，Bi3和Bi4的第一，第二，第三和第四控制信号总线，以及分别电连接的多个移位寄存器级，每个移位寄存器级具有第一和第二输入节点，其中移位寄存器级被分组为第一部分和第二部分，其中第一部分中每个移位寄存器级的第一和第二输入节点电耦合到第一部分和第二部分，分别用于接收第一和第二控制信号Bi1和Bi2的第二控制信号总线和第二部分中每个移位寄存器级的第一和第二输入节点电耦合到第三和第四控制信号总线，第三和第四控制信号Bi3和Bi4。

8. 发明申请

US20110286571A1 SHIFT REGISTER WITH EMBEDDED BIDIRECTIONAL SCANNING FUNCTION 有权
标题翻译：具有嵌入式双向扫描功能的移位寄存器
公开(公告)号：US20110286571A1
公开(公告)日：2011-11-24
申请号：US13196322
申请日：2011-08-02
申请人： Ching-Huan Lin , Sheng-Chao Liu , Kuan-Chun Huang , Chih-Hung Shih
发明人： Ching-Huan Lin , Sheng-Chao Liu , Kuan-Chun Huang , Chih-Hung Shih
IPC分类号： G11C19/00
CPC分类号： G11C19/28 , G09G3/3677
摘要： The present invention relates to a shift register having a plurality of stages electrically coupled to each other in series. Each stage includes a first and second TFT transistor. The first TFT transistor has a get electrically coupled to the output of the immediately prior stage, a drain electrically coupled to the boost point of the stage, and a source configured to receive one of the first and second control signals. The second TFT transistor has a get electrically coupled to the output of the immediately next stage, a drain and a source electrically coupled the drain and the source of the first transistor, respectively.
摘要翻译：本发明涉及一种具有彼此串联电耦合的多个级的移位寄存器。每个级包括第一和第二TFT晶体管。第一TFT晶体管被电耦合到紧邻的前级的输出，电耦合到级的升压点的漏极和被配置为接收第一和第二控制信号中的一个的源极。第二TFT晶体管被电耦合到紧邻的下一级的输出，漏极和源极分别电耦合第一晶体管的漏极和源极。

9. 发明授权

US07696972B2 Single clock driven shift register and driving method for same 有权
标题翻译：单时钟驱动移位寄存器和驱动方法相同
公开(公告)号：US07696972B2
公开(公告)日：2010-04-13
申请号：US11144939
申请日：2005-06-06
申请人： Jung-Chun Tseng , Sheng-Chao Liu , Jian-Shen Yu
发明人： Jung-Chun Tseng , Sheng-Chao Liu , Jian-Shen Yu
IPC分类号： G09G3/36
CPC分类号： G11C19/00 , G09G3/3674 , G09G3/3685 , G11C19/28
摘要： A single clock driven shift register comprising multiple stages is provided. The (M)th stage comprises a latch unit, a logic unit, and a non-overlap buffer. The latch unit latches an input signal from the (M−1)th stage according to a clock signal. The logic unit connecting to an output terminal of the latch unit deals with an output signal of the latch unit and the clock signal with an NAND logic calculation. The non-overlap buffer connecting to the output terminal of the logic unit comprises at least three inverters connected in a serial, and an output signal of the first inverter coupled to the output terminal of the logic unit is input to an latch unit of the (M+1)th stage. Meanwhile, an output signal of the non-overlap buffer of the (M−1)th stage is input to the non-overlap buffer or the logic unit to delay the output signal of the non-overlap buffer.
摘要翻译：提供包括多级的单个时钟驱动移位寄存器。第（M）级包括锁存单元，逻辑单元和非重叠缓冲器。锁存单元根据时钟信号锁存来自第（M-1）级的输入信号。连接到锁存单元的输出端的逻辑单元用NAND逻辑计算处理锁存单元的输出信号和时钟信号。连接到逻辑单元的输出端子的非重叠缓冲器包括串联连接的至少三个反相器，并且耦合到逻辑单元的输出端的第一反相器的输出信号被输入到 M + 1）级。同时，将第（M-1）级的非重叠缓冲器的输出信号输入到非重叠缓冲器或逻辑单元，以延迟非重叠缓冲器的输出信号。

10. 发明授权

US08248353B2 Method and device for reducing voltage stress at bootstrap point in electronic circuits 有权
标题翻译：用于降低电子电路自举点电压应力的方法和装置
公开(公告)号：US08248353B2
公开(公告)日：2012-08-21
申请号：US11894752
申请日：2007-08-20
申请人： Sheng-Chao Liu , Chen-Ming Chen , Ming-Tien Lin
发明人： Sheng-Chao Liu , Chen-Ming Chen , Ming-Tien Lin
IPC分类号： G09G3/36
CPC分类号： G11C19/28 , G09G3/3677 , G09G2310/0286 , G09G2330/04
摘要： A discharging device is used to reduce the voltage level at a bootstrap point in an electronic circuit such as a shift register circuit. In such a circuit, a first transistor in a conducting state receives an input pulse and conveys it to the gate terminal of a second transistor, causing the second transistor to be in a conducting state. This gate terminal is known as a bootstrap point. After receiving the input pulse, an output pulse is produced at one drain/source terminal of the second transistor. During the time period of the output pulse, the first transistor is in a non-conducting state and the voltage level at the bootstrap point is high, imposing a stress upon the first transistor. A discharging circuit consisting of at least one transistor is coupled to the bootstrap point in order to reduce the voltage level at the output pulse period.
摘要翻译：放电装置用于降低诸如移位寄存器电路的电子电路中的自举点处的电压电平。在这种电路中，导通状态的第一晶体管接收输入脉冲并将其传送到第二晶体管的栅极端子，使第二晶体管处于导通状态。该门终端被称为引导点。在接收到输入脉冲之后，在第二晶体管的一个漏极/源极端产生输出脉冲。在输出脉冲的时间周期期间，第一晶体管处于非导通状态，并且自举点处的电压电平高，对第一晶体管施加应力。由至少一个晶体管组成的放电电路耦合到自举点，以便降低输出脉冲周期的电压电平。

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