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    • 6. 发明申请
    • INTEGRATED LIGHT GUIDE PANEL AND METHOD OF MANUFACTURING THE SAME
    • 集成光导板及其制造方法
    • WO2007094558A1
    • 2007-08-23
    • PCT/KR2006/005667
    • 2006-12-22
    • DOOSAN CORPORATIONKIM, Ji-GonKOOK, Min-CheolKIM, Kwang-WonLEE, Sang-Do
    • KIM, Ji-GonKOOK, Min-CheolKIM, Kwang-WonLEE, Sang-Do
    • G02F1/13357
    • G02B6/0065G02B6/0043G02B6/0053
    • An integrated light guide panel for use in a backlight unit for an LCD and a method for manu¬ facturing the same are disclosed. The integrated light guide panel includes a light guide panel for guiding light, to form surface light, a reflective coating layer arranged beneath the light guide panel, to reflect light emerging from a lower surface of the light guide panel such that the light is again incident to the light guide panel, a diffusive coating layer arranged over the light guide panel, to diffuse light emerging from the light guide panel, a prism coating layer arranged over the diffusive coating layer, to concentrate light emerging from the diffusive coating layer, and low refractive coating layers respectively arranged between the light guide panel and the reflective coating layer and between the light guide panel and the diffusive coating layer. In accordance with this configuration, it is possible to reduce the number of assembly processes for the backlight unit, and thus to achieve improvements in workability and quality. It is also possible to prevent the generation of blemishes caused by wrinkles in optical films.
    • 公开了一种用于LCD背光单元的集成导光板及其制造方法。 集成导光板包括导光板,用于引导光,形成表面光,布置在导光板下方的反射涂层,以反射从导光板的下表面出射的光,使得光再次入射 配置在导光板上的扩散涂布层,使从导光板出射的光扩散到布置在漫射涂层上方的棱镜涂布层,使从扩散涂层出射的光集中, 分别布置在导光板和反射涂层之间以及导光板和漫射涂层之间的折射涂层。 根据该结构,能够减少背光单元的组装处理次数,能够提高可加工性和质量。 也可以防止由于光学膜中的皱纹引起的污渍的产生。
    • 8. 发明申请
    • WAFER-LEVEL CHIP SCALE PACKAGE AND METHOD FOR FABRICATING AND USING THE SAME
    • WO2005008724A3
    • 2005-01-27
    • PCT/US2004/021940
    • 2004-07-08
    • FAIRCHILD SEMICONDUCTOR CORPORATIONJOSHI, RajeevWU, Chung-LiLEE, Sang-DoCHOI, Yoon-HwaPARK, Min-HyoKIM, Ji-Hwan
    • JOSHI, RajeevWU, Chung-LiLEE, Sang-DoCHOI, Yoon-HwaPARK, Min-HyoKIM, Ji-Hwan
    • H01L21/60H01L23/31H01L23/485H01L23/525
    • First, second, and third packaged semiconductor devices (a wafer-level chip scale package) are described. The first packaged semiconductor device contains no UBM between a chip pad and an RDL pattern. The first device contains only a single non-polymeric insulation layer between the RDL pattern and the solder bump, where the insulation layer does not need high temperature curing processes and so does not induce thermal stresses into the device. Manufacturing costs for the first device are diminished by eliminating the UBM between the chip pad and the RDL pattern. The second packaged semiconductor device (a second wafer-level chip scale package) contains an adhesive film containing conductive particles sandwiched between a chip with Cu-based stud bumps and a substrate containing a bond pad. Some conductive particles are sandwiched between the stud bump and bond pad to create a conductive path. The second device is manufactured without the steps of dispensing solder and reflowing the solder and can optionally eliminate the use of a redistribution trace. Using such a configuration increases the reliability of the second wafer-level chip scale package. The third packaged semiconductor device (a third wafer-level chip scale package) contains a conductive adhesive material as an electrical interconnect route between the semiconductor die and a patterned conductive substrate. The patterned conductive substrate acts not only as a substrate, but also as a redistribution layer that converts the dense pad layout of the die to a larger array configuration of the solder balls in the circuit board. Using the invention allows the formation of a lower priced chip scale package that overcomes the restriction of the die size used in die-sized chip packages and the input-output pattern that can be required by the printed circuit board. Thus, the invention can provide a familiar pitch (i.e., interface) to the printed circuit board for any small die.