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1. 外观设计

USD666705S1 Wick 有权
公开(公告)号：USD666705S1
公开(公告)日：2012-09-04
申请号：US29369532
申请日：2010-09-09
申请人： Daniel A. Andersen , Kylie L. Levake , Kenneth W. Michaels , David J. Schram , Nitin Sharma , James T. Walker , Steven V. Bisbikis , Jason R. Gebhardt
设计人： Daniel A. Andersen , Kylie L. Levake , Kenneth W. Michaels , David J. Schram , Nitin Sharma , James T. Walker , Steven V. Bisbikis , Jason R. Gebhardt

2. 外观设计

USD674475S1 Wick 有权
公开(公告)号：USD674475S1
公开(公告)日：2013-01-15
申请号：US29428004
申请日：2012-07-25
申请人： Daniel A. Andersen , Kylie L. Levake , Kenneth W. Michaels , David J. Schram , Nitin Sharma , James T. Walker , Steven V. Bisbikis , Jason R. Gebhardt
设计人： Daniel A. Andersen , Kylie L. Levake , Kenneth W. Michaels , David J. Schram , Nitin Sharma , James T. Walker , Steven V. Bisbikis , Jason R. Gebhardt

3. 发明授权

US08378689B2 Electrostatic sensor device and matrix 有权
标题翻译：静电传感器和矩阵
公开(公告)号：US08378689B2
公开(公告)日：2013-02-19
申请号：US12836365
申请日：2010-07-14
申请人： James T. Walker , Christopher I. Walker , Tony G. Tadin , Arjen Sundman
发明人： James T. Walker , Christopher I. Walker , Tony G. Tadin , Arjen Sundman
IPC分类号： G01R31/02 , G01R29/22
CPC分类号： G01R29/12
摘要： An electrostatic sensor device including a first sensor element and a second sensor element; a dielectric substrate material formed in two layers, and a sensing hole which penetrates the dielectric substrate material from its upper surface to its lower surface. The first sensor element is receivable in the sensing hole; and second sensor element includes a first conducting ring disposed on an upper surface of said dielectric substrate and surrounding said sensing hole. The second conducting ring is disposed on a lower surface of the dielectric substrate and surrounds the sensing hole. The first sensor element and the second sensor are capable of producing a variable response when the first sensor element is disposed in the sensing hole.
摘要翻译：一种静电传感器装置，包括第一传感器元件和第二传感器元件; 形成为两层的电介质基板材料，以及从上表面向下表面贯通电介质基板材料的检测孔。第一传感器元件可接收在传感孔中; 并且第二传感器元件包括设置在所述电介质基板的上表面上并围绕所述感测孔的第一导电环。第二导电环设置在电介质基板的下表面上，并围绕传感孔。当第一传感器元件设置在感测孔中时，第一传感器元件和第二传感器能够产生可变响应。

4. 发明授权

US07554378B2 Fast DC coupled level translator 有权
标题翻译：快速直流耦合电平转换器
公开(公告)号：US07554378B2
公开(公告)日：2009-06-30
申请号：US11766701
申请日：2007-06-21
申请人： James T. Walker
发明人： James T. Walker
IPC分类号： H03L5/00 , H03K5/22
CPC分类号： H03K19/01707 , H03K19/018521
摘要： A level translator has an inverter comprising a first transistor having a first predetermined voltage threshold and a second transistor having a second predetermined voltage threshold. The two transistors have control gates being of complementary conductivity. A first capacitor is connected at one end to the gate of the first transistor and at a second end to an input signal. A second capacitor is connected at one end to the gate of the second transistor, the input signal being applied to a second end of the second capacitor. A comparator is used for detecting the relationship between the input signal and a reference voltage. A first current mirror has one terminal connected to an output of the comparator, and another terminal connected to the gate of the first transistor. A second current mirror has one terminal connected to an output of the comparator, and another terminal connected to the gate of the second transistor. A first clamp circuit is used for limiting a gate voltage of said first transistor. A second clamp circuit is used for limiting a gate voltage of said second transistor.
摘要翻译：电平转换器具有包括具有第一预定电压阈值的第一晶体管和具有第二预定电压阈值的第二晶体管的反相器。两个晶体管具有互补导电性的控制栅极。第一电容器的一端连接到第一晶体管的栅极，在第二端连接到输入信号。第二电容器的一端连接到第二晶体管的栅极，输入信号被施加到第二电容器的第二端。比较器用于检测输入信号和参考电压之间的关系。第一电流镜具有连接到比较器的输出的一个端子，以及连接到第一晶体管的栅极的另一个端子。第二电流镜具有连接到比较器的输出的一个端子，以及连接到第二晶体管的栅极的另一个端子。第一钳位电路用于限制所述第一晶体管的栅极电压。第二钳位电路用于限制所述第二晶体管的栅极电压。

5. 发明授权

US06552591B1 Method and apparatus for processing a wide dynamic range signal 失效
标题翻译：用于处理宽动态范围信号的方法和装置
公开(公告)号：US06552591B1
公开(公告)日：2003-04-22
申请号：US10002902
申请日：2001-11-01
申请人： Kamran Khorram Abadi , James T. Walker , Robert Gustav Lorenz
发明人： Kamran Khorram Abadi , James T. Walker , Robert Gustav Lorenz
IPC分类号： H04B116
CPC分类号： H03G7/06 , H04B1/109
摘要： Method and apparatus are provided for processing a wide dynamic range analog signal which comprises a compressive nonlinear transfer function responsive to the average amplitude of the signal without feedback along the signal path. The invention employs frequency selective filtering and expansion of the compressed signal. The invention is applicable to any analog signal system having a plurality of channels carrying related signal information.
摘要翻译：提供了用于处理宽动态范围模拟信号的方法和装置，其包括响应于信号的平均幅度的压缩非线性传递函数，而不沿信号路径反馈。本发明采用频率选择滤波和压缩信号的扩展。本发明可应用于具有携带相关信号信息的多个信道的任何模拟信号系统。

6. 发明授权

US09100008B2 Bootstrapped switch with a highly linearized resistance 有权
标题翻译：引导开关具有高度线性化的电阻
公开(公告)号：US09100008B2
公开(公告)日：2015-08-04
申请号：US13526092
申请日：2012-06-18
申请人： Benedict C. K. Choy , James T. Walker , Ming-Yuan Yeh
发明人： Benedict C. K. Choy , James T. Walker , Ming-Yuan Yeh
IPC分类号： H03K17/16 , H03K17/06
CPC分类号： H03K17/063 , H03K17/163
摘要： Systems and methods are disclosed for operating a highly linearized resistance for a switch through use of a bootstrapped features. In one exemplary implementation, there is provided a method and system that implements a method for operating a circuit configured to provide a highly linearized resistance including receiving a signal via a bootstrapped switch, coupling the received signal to a gate if the received signal is high, receiving a signal via a switch control input coupled to a high impedance element. Moreover, the method includes coupling the high impedance element to the gate and turning off the switch via a gate turn off when the gate turn off pulls the gate low.
摘要翻译：公开了用于通过使用自举特征来操作用于开关的高度线性化电阻的系统和方法。在一个示例性实施方式中，提供了一种方法和系统，其实现用于操作被配置为提供高度线性化电阻的电路的方法，所述电路包括经由自举交换器接收信号，如果接收信号为高，则将接收信号耦合到门，通过耦合到高阻抗元件的开关控制输入来接收信号。此外，该方法包括将高阻抗元件耦合到栅极并且当栅极关断将栅极拉低时通过栅极截止来关断开关。

7. 发明申请

US20120268012A1 CIRCUIT FOR DETECTION AND CONTROL OF LED STRING OPERATION 有权
标题翻译： LED灯操作检测和控制电路
公开(公告)号：US20120268012A1
公开(公告)日：2012-10-25
申请号：US13451457
申请日：2012-04-19
申请人： James T. Walker
发明人： James T. Walker
IPC分类号： H05B37/02 , H05B37/03
CPC分类号： H05B33/0893
摘要： A circuit is disclosed for determining which of a multiplicity of LED strings in an illumination system has a fault. A group of circuits determines the maximum, minimum, midpoint between maximum and minimum, and average voltage of the group of LED string voltages in use, and examines the statistical properties of the LED string voltages. Comparators are used to find the strings which have the highest and lowest operating voltages, and to compare the midpoint and average voltages to determine whether the highest or lowest voltage string is responsible for causing a fault in the illumination system operation. Memory means are used to keep the said determined string turned off to prevent faulty operation.
摘要翻译：公开了一种用于确定照明系统中多个LED串中的哪一个具有故障的电路。一组电路确定最大值和最小值之间的最大值，最小值，最小值以及所使用的LED串电压组的平均电压，并检查LED串电压的统计特性。比较器用于找到具有最高和最低工作电压的串，并且比较中点和平均电压以确定最高或最低电压串是否导致照明系统操作中的故障。存储装置用于保持所述确定的字符串被关闭以防止错误的操作。

8. 发明授权

US07564263B2 High-speed logic signal level shifter 有权
标题翻译：高速逻辑信号电平转换器
公开(公告)号：US07564263B2
公开(公告)日：2009-07-21
申请号：US11379509
申请日：2006-04-20
申请人： James T. Walker , Jimes Lei
发明人： James T. Walker , Jimes Lei
IPC分类号： H03K19/0175
CPC分类号： H03K3/356113
摘要： A high speed logic signal level shifter is comprised of: a logic signal buffer for receiving logic signal information and having true and complement state differential outputs; a binary flip-flop circuit with set and reset inputs; a first coupling capacitor connected from the true buffer output to the set input of the binary flip-flop circuit; and a second coupling capacitor connected from the complement buffer output to the reset input of the binary flip-flop circuit. The high speed logic signal level shifter transfers a fast logic signal across a high voltage difference by making use of rapid voltage changes transmitted through small capacitors. The signal changes carried by the capacitors are about 10 times faster than any expected voltage transient on VPP or VNN. Furthermore, the differential coupling circuit is used to provide enhanced protection against undesired circuit switching during supply voltage changes.
摘要翻译：高速逻辑信号电平移位器包括：逻辑信号缓冲器，用于接收逻辑信号信息并具有真和补状态差分输出; 具有置位和复位输入的二进制触发器电路; 从真实缓冲器输出端连接到二进制触发器电路的设定输入端的第一耦合电容器; 以及从补码缓冲器输出连接到二进制触发器电路的复位输入的第二耦合电容器。高速逻辑信号电平转换器通过利用通过小电容器传输的快速电压变化，在高电压差之间传输快速逻辑信号。电容器所带来的信号变化比VPP或VNN上任何预期的电压瞬变快10倍。此外，差分耦合电路用于在电源电压变化期间提供增强的防止不期望的电路切换的保护。

9. 发明授权

US07538581B2 Fast AC coupled level translator 有权
标题翻译：快速AC耦合电平转换器
公开(公告)号：US07538581B2
公开(公告)日：2009-05-26
申请号：US11831011
申请日：2007-07-31
申请人： James T. Walker
发明人： James T. Walker
IPC分类号： H03K19/094
CPC分类号： H03K3/356104
摘要： A level translator has a pair of transistors, wherein a first transistor of the pair of transistors and a second transistor of the pair of transistors are complimentary. A pair of capacitors are provided, wherein a first capacitor of the pair of capacitors is coupled to a voltage input VIN and to a gate of a first transistor of the pair of complimentary transistors and a second capacitor of the pair of capacitors is coupled the voltage input VIN and to a gate of a second transistor of the pair of complimentary transistors. A flip flop device is provided having a first input coupled to a drain of the first transistor, and a second input coupled to a drain of the second transistor. A pair of resistors is provided, wherein a first resistor of the pair of resistors is coupled to the gate of the first transistor and to a voltage supply of VDD, and a second resistor of the pair of resistors is coupled to the gate of the second transistor and to a voltage supply VSS. A pair of clamping circuits is provided, wherein a first clamping circuit of the pair of clamping circuits is coupled to the gate of the first transistor and to a voltage supply of VDD, and a second clamping circuit of the pair of clamping circuits is coupled to the gate of the second transistor and to a voltage supply VSS.
摘要翻译：电平转换器具有一对晶体管，其中该对晶体管中的第一晶体管和该对晶体管的第二晶体管是互补的。提供了一对电容器，其中该对电容器中的第一电容器耦合到电压输入端VIN和一对互补晶体管的第一晶体管的栅极，并且该对电容器的第二电容器耦合电压输入VIN和该对互补晶体管的第二晶体管的栅极。提供了具有耦合到第一晶体管的漏极的第一输入和耦合到第二晶体管的漏极的第二输入的触发器装置。提供了一对电阻器，其中该对电阻器的第一电阻器耦合到第一晶体管的栅极和VDD的电压源，并且该对电阻器的第二电阻器耦合到第二晶体管的栅极晶体管和电压源VSS。提供了一对钳位电路，其中该对钳位电路的第一钳位电路耦合到第一晶体管的栅极和VDD的电压源，并且该对钳位电路的第二钳位电路耦合到第二晶体管的栅极和电压源VSS。

10. 发明申请

US20070296348A1 CURRENT DRIVEN BIPOLAR HIGH VOLTAGE DRIVER FOR CAPACITIVE LOADS 有权
标题翻译：目前用于电容负载的双极性高压驱动器
公开(公告)号：US20070296348A1
公开(公告)日：2007-12-27
申请号：US11762901
申请日：2007-06-14
申请人： James T. Walker
发明人： James T. Walker
IPC分类号： H05B39/04
CPC分类号： H05B33/08 , H02M3/073
摘要： A circuit for generating a high voltage alternating current to drive a load has a current source having a first terminal and a second terminal. The circuit further has an output terminal and a circuit ground terminal. A first switch will conduct between the first terminal of the current source and the circuit ground terminal when the first switch is closed. A second switch will conduct between the first terminal of the current source and the output terminal when the second switch is closed. A third switch will conduct between the second terminal of the current source and the circuit ground terminal when the third switch is closed. A fourth switch will conduct between the second terminal of the current source and the output terminal when the fourth switch is closed. A load is coupled to the output terminal and the circuit ground terminal.
摘要翻译：用于产生用于驱动负载的高压交流电的电路具有具有第一端子和第二端子的电流源。电路还具有输出端子和电路接地端子。当第一开关闭合时，第一开关将在电流源的第一端和电路接地端之间导通。当第二开关闭合时，第二开关将在电流源的第一端子和输出端子之间导通。当第三开关闭合时，第三开关将在电流源的第二端子与电路接地端子之间导通。当第四开关闭合时，第四开关将在电流源的第二端子与输出端子之间导通。负载耦合到输出端子和电路接地端子。

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