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1. 发明申请

US20120254700A1 MECHANISMS AND TECHNIQUES FOR PROVIDING CACHE TAGS IN DYNAMIC RANDOM ACCESS MEMORY 有权
标题翻译：在动态随机存取存储器中提供缓存标签的机制和技术
公开(公告)号：US20120254700A1
公开(公告)日：2012-10-04
申请号：US13078704
申请日：2011-04-01
申请人： Darrell S. McGinnis , C. Scott Huddleston , Rajat Agarwal , Meenakshisundara R. Chinthamani
发明人： Darrell S. McGinnis , C. Scott Huddleston , Rajat Agarwal , Meenakshisundara R. Chinthamani
IPC分类号： H03M13/05 , G06F12/02 , G06F11/10
CPC分类号： G06F12/0893 , G06F11/1064 , G06F2212/6012 , H03M13/033 , H03M13/19 , H03M13/6527
摘要： A dynamic random access memory (DRAM) is operated as a cache memory coupled with a processor core. A block of data is transmitted to the DRAM as even and odd pairs of bits from the processor core. The block of data includes N error correcting code (ECC) bits and 11*N data bits. Two or more cache lines are to be stored in a memory page with tag bits aggregated together within the page.
摘要翻译：动态随机存取存储器（DRAM）作为与处理器核心耦合的高速缓冲存储器来操作。将数据块作为来自处理器核心的偶数和奇数对位传送到DRAM。数据块包括N个纠错码（ECC）位和11 * N个数据位。将两条或更多条高速缓存行存储在存储器页面中，其中标签位在页面内聚合在一起。

2. 发明授权

US08612832B2 Mechanisms and techniques for providing cache tags in dynamic random access memory 有权
标题翻译：在动态随机存取存储器中提供缓存标签的机制和技术
公开(公告)号：US08612832B2
公开(公告)日：2013-12-17
申请号：US13078704
申请日：2011-04-01
申请人： Darrell S. McGinnis , C. Scott Huddleston , Rajat Agarwal , Meenakshisundaram R. Chinthamani
发明人： Darrell S. McGinnis , C. Scott Huddleston , Rajat Agarwal , Meenakshisundaram R. Chinthamani
IPC分类号： G11C29/00
CPC分类号： G06F12/0893 , G06F11/1064 , G06F2212/6012 , H03M13/033 , H03M13/19 , H03M13/6527
摘要： A dynamic random access memory (DRAM) is operated as a cache memory coupled with a processor core. A block of data is transmitted to the DRAM as even and odd pairs of bits from the processor core. The block of data includes N error correcting code (ECC) bits and 11*N data bits. Two or more cache lines are to be stored in a memory page with tag bits aggregated together within the page.
摘要翻译：动态随机存取存储器（DRAM）作为与处理器核心耦合的高速缓冲存储器来操作。将数据块作为来自处理器核心的偶数和奇数对位传送到DRAM。数据块包括N个纠错码（ECC）位和11 * N个数据位。将两条或更多条高速缓存行存储在存储器页面中，其中标签位在页面内聚合在一起。

3. 发明授权

US06956775B1 Write pointer error recovery 失效
标题翻译：写指针错误恢复
公开(公告)号：US06956775B1
公开(公告)日：2005-10-18
申请号：US10749467
申请日：2003-12-31
申请人： Derek A. Thompson , Darrell S. McGinnis , Steve A. McKinnon , John Zumkehr
发明人： Derek A. Thompson , Darrell S. McGinnis , Steve A. McKinnon , John Zumkehr
IPC分类号： G11C8/10 , G11C16/04
CPC分类号： G11C8/10
摘要： A write pointer (21) from a write pointer circuit (13) may cause a demultiplexer circuit (12) to direct data from a memory cell (11A–11N) to a desired bit location (0–4) in a register 14. A read pointer (20) may cause a multiplexer circuit (15) to select data from a desired bit location in the register to provide as output data (19) or to select one of the bits of the write pointer. The write pointer may be incremented by a data strobe signal (17). The state of the write pointer may be determined by reading the bits of the write pointer, and the write pointer may be synchronized via a reset line (18).
摘要翻译：来自写指针电路（13）的写指针（21）可以使解复用器电路（12）将数据从存储器单元（11A-11N）引导到寄存器14中的期望位位置（0-4）读指针（20）可以使多路复用器电路（15）从寄存器中的期望位位置中选择数据，以提供作为输出数据（19）或者选择写指针的位之一。写指针可以被数据选通信号（17）递增。可以通过读取写指针的位来确定写指针的状态，并且可以经由复位线（18）来同步写指针。

4. 发明授权

US07177989B1 Retry of a device read transaction 有权
标题翻译：重试设备读取事务
公开(公告)号：US07177989B1
公开(公告)日：2007-02-13
申请号：US10749924
申请日：2003-12-31
申请人： Darrell S. McGinnis
发明人： Darrell S. McGinnis
IPC分类号： G06F12/06
CPC分类号： G06F11/141
摘要： An apparatus (11) causes invalid data to be read again from a memory device (12, 13) before being read by a device (10). A transaction queue (22) stores pending and dispatched device transactions, the queue includes an input for receiving (21) transactions, an output for dispatching (26) transactions, a pointer for pending transactions, and a pointer for dispatched transactions. A master controller (42) responds to an invalid data signal by preventing the transaction queue from dispatching pending transactions to the memory device, by causing the transaction queue to dispatch again the device read transaction which resulted in the invalid data and, subsequently, by causing the data which was read again from the memory device to be accepted by the destination device, by setting the dispatched transaction pointer to the pending transactions pointer, and by enabling the transaction queue to dispatch pending transactions to the memory device.
摘要翻译：在由设备（10）读取之前，设备（11）使得从存储器设备（12,13）再次读取无效数据。交易队列（22）存储待处理和分派的设备事务，该队列包括用于接收（21）事务的输入，用于调度（26）事务的输出，用于未决事务的指针，以及用于发送的事务的指针。主控制器（42）通过防止事务队列将待处理事务分配到存储器设备来响应无效数据信号，通过使事务队列再次发送导致无效数据的设备读取事务，并且随后通过引起通过将分配的事务指针设置为待处理事务指针，以及通过使事务队列将待处理的事务分派到存储器设备，从存储器件再次读取以被目标设备接受的数据。

5. 发明授权

US07127584B1 System and method for dynamic rank specific timing adjustments for double data rate (DDR) components 失效
标题翻译：用于双倍数据速率（DDR）组件的动态等级特定时序调整的系统和方法
公开(公告)号：US07127584B1
公开(公告)日：2006-10-24
申请号：US10713718
申请日：2003-11-14
申请人： Derek A. Thompson , Darrell S. McGinnis , John F. Zumkehr
发明人： Derek A. Thompson , Darrell S. McGinnis , John F. Zumkehr
IPC分类号： G06F12/00
CPC分类号： G11C7/1051 , G11C7/1066 , G11C7/1072
摘要： In some embodiments, a system and method for making rank-specific adjustments to the READ tenure parameters of a double data-rate (DDR) memory component to improve the DDR bus timing margins. When a READ tenure is encountered for the DDR memory component, the rank of the DDR memory component is calculated and the value is used to retrieve two adjustment signals, which are specific to the DDR memory component, from the look up table. One of the adjustment signals is used to adjust a gating signal for the data strobe signal of the component. The other adjustment signal is used to fine tune a required ¼ clock delay for the data strobe signal to read the data from the DDR memory component while adjusting for the inherent latency of the DDR memory component. Other embodiments are described and claimed.
摘要翻译：在一些实施例中，一种用于对双数据速率（DDR）存储器组件的读取权限参数进行排名特定调整以提高DDR总线时序余量的系统和方法。当DDR存储器组件遇到读取权限时，计算DDR存储器组件的等级，该值用于从查找表中检索DDR存储器组件特有的两个调整信号。其中一个调整信号用于调整组件的数据选通信号的选通信号。其他调整信号用于微调数据选通信号所需的1/4时钟延迟，以便在调整DDR存储器组件的固有延迟时从DDR存储器组件中读取数据。描述和要求保护其他实施例。

6. 发明授权

US07249274B1 System and method for scalable clock gearing mechanism 有权
标题翻译：可伸缩时钟齿轮传动机构的系统和方法
公开(公告)号：US07249274B1
公开(公告)日：2007-07-24
申请号：US10748836
申请日：2003-12-30
申请人： Darrell S. McGinnis
发明人： Darrell S. McGinnis
IPC分类号： G06F1/12
CPC分类号： G06F1/12 , G06F1/08
摘要： In some embodiments, a system and method for making a scalable clock gearing mechanism may allow multiple devices operating on different clock speeds to communicate. In an embodiment, a mechanism may be used to input data clocked on a first clock frequency and output the data on a second clock frequency. The mechanism may temporarily store the data until the next clock cycle of the second clock. Further, the mechanism may make use of multiple inputs or outputs to input or output multiple data units during a single clock cycle to keep the delay between the arrival and departure of the data small.
摘要翻译：在一些实施例中，用于制造可伸缩时钟齿轮传动机构的系统和方法可允许以不同时钟速度工作的多个设备进行通信。在一个实施例中，可以使用机制来输入以第一时钟频率计时的数据，并以第二时钟频率输出数据。该机制可以临时存储数据直到第二个时钟的下一个时钟周期。此外，该机制可以利用多个输入或输出来在单个时钟周期期间输入或输出多个数据单元，以保持数据的到达和离开之间的延迟较小。

7. 发明授权

US07133960B1 Logical to physical address mapping of chip selects 有权
标题翻译：逻辑到物理地址映射的芯片选择
公开(公告)号：US07133960B1
公开(公告)日：2006-11-07
申请号：US10749464
申请日：2003-12-31
申请人： Derek A. Thompson , Darrell S. McGinnis , Steve A. McKinnon
发明人： Derek A. Thompson , Darrell S. McGinnis , Steve A. McKinnon
IPC分类号： G06F12/06
CPC分类号： G06F12/0623 , G06F12/0653
摘要： In some embodiments, a system and method for mapping the logical chip selects to a physical chip select. A chip select remapping unit receives logical chip select associated with a dual in-line memory module. The chip select remapping unit converts the logical chip select vector through a redirection table that maps the logical memory ranks to available physical memory ranks.
摘要翻译：在一些实施例中，用于将逻辑芯片选择映射到物理芯片选择的系统和方法。芯片选择重映射单元接收与双列直插存储器模块相关联的逻辑芯片选择。芯片选择重映射单元通过将逻辑内存等级映射到可用物理内存等级的重定向表来转换逻辑片选择向量。

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