专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06631429B2 Real-time processing of a synchronous or isochronous data stream in the presence of gaps in the data stream due to queue underflow or overflow 失效
标题翻译：在存在由于队列下溢或溢出引起的数据流中的间隙的同步或等时数据流的实时处理
公开(公告)号：US06631429B2
公开(公告)日：2003-10-07
申请号：US09471942
申请日：1999-12-23
申请人： Erik C. Cota-Robles , Barry O'Mahony , Alberto J. Martinez
发明人： Erik C. Cota-Robles , Barry O'Mahony , Alberto J. Martinez
IPC分类号： G06F1300
CPC分类号： H04L12/64 , H04L25/05
摘要： In one embodiment of the present invention, an output device sends a spurious data sample in place of a first data sample to be sent from a queue if the queue is in a state of underflow during which the first data sample is not available to be sent. The buffer is to store data samples for an isochronous data transmission. Circuitry skips the first data sample when the first data sample becomes available in the queue so that synchronization for subsequent data samples sent from the queue is preserved. In another embodiment of the present invention, an input device advances an input buffer pointer to point to a next location in a memory in response to receiving a data sample at a queue during a state of overflow. The input buffer pointer indicates a location in the memory to which a next data sample is to be sent from the queue. The queue stores data samples for an isochronous data transmission. By advancing the input buffer pointer, synchronization for subsequent data samples is preserved.
摘要翻译：在本发明的一个实施例中，如果队列处于下溢状态，则第一数据样本不可用于发送，则输出设备发送伪数据样本代替要从队列发送的第一数据样本。缓冲区用于存储用于同步数据传输的数据样本。当第一个数据样本在队列中可用时，电路会跳过第一个数据样本，以便保留从队列发送的后续数据样本的同步。在本发明的另一实施例中，响应于在溢出状态期间在队列处接收到数据样本，输入装置使输入缓冲器指针前进到指向存储器中的下一个位置。输入缓冲区指针指示要从队列发送下一个数据样本的存储器中的位置。队列存储用于等时数据传输的数据样本。通过前进输入缓冲区指针，保留后续数据样本的同步。

2. 发明授权

US07797699B2 Method and apparatus for scheduling virtual machine access to shared resources 有权
标题翻译：调度虚拟机访问共享资源的方法和装置
公开(公告)号：US07797699B2
公开(公告)日：2010-09-14
申请号：US10947902
申请日：2004-09-23
申请人： Alain Kagi , Andrew V. Anderson , Steven M. Bennett , Erik C. Cota-Robles , Gregory M. Jablonski
发明人： Alain Kagi , Andrew V. Anderson , Steven M. Bennett , Erik C. Cota-Robles , Gregory M. Jablonski
IPC分类号： G06F9/455 , G06F9/46 , G06F3/00
CPC分类号： G06F9/5011
摘要： A method for managing IO requests from a virtual machine to access IO resources on a physical machine includes determining a request priority associated with an IO request. The IO request is placed in an appropriate queue in response to determining the request priority.
摘要翻译：用于管理来自虚拟机的IO请求以访问物理机器上的IO资源的方法包括确定与IO请求相关联的请求优先级。响应于确定请求优先级，IO请求被放置在适当的队列中。

3. 发明授权

US08819699B2 Controlling virtual machines based on performance counters 有权
标题翻译：基于性能计数器控制虚拟机
公开(公告)号：US08819699B2
公开(公告)日：2014-08-26
申请号：US11618446
申请日：2006-12-29
申请人： Erik C. Cota-Robles , Steven M. Bennett , Andrew V. Anderson , Sebastian Schoenberg
发明人： Erik C. Cota-Robles , Steven M. Bennett , Andrew V. Anderson , Sebastian Schoenberg
IPC分类号： G06F3/00 , G06F9/44 , G06F9/46 , G06F13/00
CPC分类号： G06F9/45558 , G06F2009/45566
摘要： Embodiments of apparatuses, methods, and systems for controlling virtual machines based on performance counters are disclosed. In one embodiment, an apparatus includes an event counter, a comparator, and virtualization control logic. The event counter is to keep an event count based on the number of occurrences of an event. The comparator is to determine whether the event count has reached a threshold value. The virtualization control logic is to transfer control of the apparatus from a guest to a host in response to the comparator determining that the event count has reached the threshold value.
摘要翻译：公开了用于基于性能计数器来控制虚拟机的设备，方法和系统的实施例。在一个实施例中，装置包括事件计数器，比较器和虚拟化控制逻辑。事件计数器是根据事件的发生次数来保持事件计数。比较器是确定事件计数是否达到阈值。响应于比较器确定事件计数已经达到阈值，虚拟化控制逻辑是将设备从客户机的控制传送到主机。

4. 发明授权

US07793286B2 Methods and systems to manage machine state in virtual machine operations 有权
标题翻译：在虚拟机操作中管理机器状态的方法和系统
公开(公告)号：US07793286B2
公开(公告)日：2010-09-07
申请号：US10324591
申请日：2002-12-19
申请人： Steven M. Bennett , Gilbert Neiger , Erik C. Cota-Robles , Stalinselvaraj Jeyasingh , Alain Kagi , Michael A. Kozuch , Richard A. Uhlig
发明人： Steven M. Bennett , Gilbert Neiger , Erik C. Cota-Robles , Stalinselvaraj Jeyasingh , Alain Kagi , Michael A. Kozuch , Richard A. Uhlig
IPC分类号： G06F9/46 , G06F9/455
CPC分类号： G06F9/45558 , G06F2009/4557
摘要： Methods and systems are provided to control transitions between a virtual machine (VM) and Virtual Machine Monitor (VMM). A processor uses state action indicators to load and/or store associated elements of machine state before completing the transition. The state action indicators may be stored in a Virtual Machine Control Structure (VMCS), predetermined, and/or calculated dynamically. In some embodiments, the values loaded can be directly acquired from the VMCS, predetermined and/or calculated dynamically. In some embodiments, the values stored may be acquired directly from machine state, predetermined and/or calculated dynamically.
摘要翻译：提供了方法和系统来控制虚拟机（VM）和虚拟机监视器（VMM）之间的转换。在完成转换之前，处理器使用状态动作指示器来加载和/或存储机器状态的相关元件。状态动作指示符可以存储在虚拟机控制结构（VMCS）中，预定的和/或动态地计算。在一些实施例中，可以从VMCS直接获取加载的值，预先确定和/或动态地计算。在一些实施例中，存储的值可以直接从机器状态获取，预定和/或动态地计算。

5. 发明授权

US08286162B2 Delivering interrupts directly to a virtual processor 有权
标题翻译：将中断直接传递到虚拟处理器
公开(公告)号：US08286162B2
公开(公告)日：2012-10-09
申请号：US11323114
申请日：2005-12-30
申请人： Gilbert Neiger , Rajesh Sankaran Madukkarumukumana , Richard A. Uhlig , Udo Steinberg , Sebastian Schoenberg , Sridhar Muthrasanallur , Steven M. Bennett , Andrew V. Anderson , Erik C. Cota-Robles
发明人： Gilbert Neiger , Rajesh Sankaran Madukkarumukumana , Richard A. Uhlig , Udo Steinberg , Sebastian Schoenberg , Sridhar Muthrasanallur , Steven M. Bennett , Andrew V. Anderson , Erik C. Cota-Robles
IPC分类号： G06F9/445 , G06F9/46 , G06F13/24 , G06F13/26 , G06F3/00 , G06F13/00
CPC分类号： G06F13/24 , G06F9/45533 , G06F9/4812
摘要： Embodiments of apparatuses, methods, and systems for delivering an interrupt to a virtual processor are disclosed. In one embodiment, an apparatus includes an interface to receive an interrupt request, delivery logic, and exit logic. The delivery logic is to determine, based on an attribute of the interrupt request, whether the interrupt request is to be delivered to the virtual processor. The exit logic is to transfer control to a host if the delivery logic determines that the interrupt request is not to be delivered to the virtual processor.
摘要翻译：公开了用于向虚拟处理器递送中断的装置，方法和系统的实施例。在一个实施例中，装置包括用于接收中断请求，传递逻辑和退出逻辑的接口。交付逻辑是基于中断请求的属性来确定中断请求是否被传送到虚拟处理器。如果传递逻辑确定中断请求不被传送到虚拟处理器，则出口逻辑是将控制传送到主机。

6. 发明申请

US20120117300A1 INVALIDATING TRANSLATION LOOKASIDE BUFFER ENTRIES IN A VIRTUAL MACHINE (VM) SYSTEM 有权
标题翻译：在虚拟机（VM）系统中隐藏翻译预览缓冲区入口
公开(公告)号：US20120117300A1
公开(公告)日：2012-05-10
申请号：US12959109
申请日：2010-12-02
申请人： Erik C. Cota-Robles , Andy Glew , Stalinselvaraj Jeyasingh , Alain Kagi , Michael A. Kozuch , Gilbert Neiger , Richard Uhlig
发明人： Erik C. Cota-Robles , Andy Glew , Stalinselvaraj Jeyasingh , Alain Kagi , Michael A. Kozuch , Gilbert Neiger , Richard Uhlig
IPC分类号： G06F12/08
CPC分类号： G06F12/1027 , G06F9/30076 , G06F12/1036 , G06F2212/151
摘要： One embodiment of the present invention is a technique to invalidate entries in a translation lookaside buffer (TLB). A TLB in a processor has a plurality of TLB entries. Each TLB entry is associated with a virtual machine extension (VMX) tag word indicating if the associated TLB entry is invalidated according to a processor mode when an invalidation operation is performed. The processor mode is one of execution in a virtual machine (VM) and execution not in a virtual machine. The invalidation operation belongs to a non-empty set of invalidation operations composed of a union of (1) a possibly empty set of operations that invalidate a variable number of TLB entries, (2) a possibly empty set of operations that invalidate exactly one TLB entry, (3) a possibly empty set of operations that invalidate the plurality of TLB entries, (4) a possibly empty set of operations that enable and disable use of virtual memory, and (5) a possibly empty set of operations that configure physical address size, page size or other virtual memory system behavior in a manner that changes the manner in which a physical machine interprets the TLB entries.
摘要翻译：本发明的一个实施例是使翻译后备缓冲器（TLB）中的条目无效的技术。处理器中的TLB具有多个TLB条目。当执行无效操作时，每个TLB条目与虚拟机扩展（VMX）标签字相关联，指示相关联的TLB条目是否根据处理器模式而无效。处理器模式是虚拟机（VM）中的执行之一，而不是虚拟机中的执行。无效操作属于一个无效的无效操作集合，它由（1）可能为空的操作集合组合，使一组可变数量的TLB条目无效，（2）一组可能的空白操作，使一个TLB无效条目，（3）使多个TLB条目无效的可能的一组操作，（4）启用和禁用虚拟存储器的使用的可能的一组可能的空操作，以及（5）配置物理的可能的一组操作地址大小，页面大小或其他虚拟内存系统行为，以改变物理机器解释TLB条目的方式。

7. 发明授权

US07318141B2 Methods and systems to control virtual machines 有权
标题翻译：控制虚拟机的方法和系统
公开(公告)号：US07318141B2
公开(公告)日：2008-01-08
申请号：US10322003
申请日：2002-12-17
申请人： Steve M. Bennett , Gilbert Neiger , Erik C. Cota-Robles , Stalinselvaraj Jeyasingh , Alain Kagi , Michael A. Kozuch , Richard A. Uhlig , Larry Smith , Dion Rodgers , Andrew Glew , Erich Boleyn
发明人： Steve M. Bennett , Gilbert Neiger , Erik C. Cota-Robles , Stalinselvaraj Jeyasingh , Alain Kagi , Michael A. Kozuch , Richard A. Uhlig , Larry Smith , Dion Rodgers , Andrew Glew , Erich Boleyn
IPC分类号： G06F12/06
CPC分类号： G06F9/45558 , G06F2009/45591
摘要： Methods and systems are provided to control the execution of a virtual machine (VM). A VM Monitor (VMM) accesses VM Control Structures (VMCS) indirectly through access instructions passed to a processor. In one embodiment, the access instructions include VMCS component identifiers used by the processor to determine the appropriate storage location for the VMCS components. The processor identifies the appropriate storage location for the VMCS component within the processor storage or within memory.
摘要翻译：提供了方法和系统来控制虚拟机（VM）的执行。 VM监视器（VMM）通过传递给处理器的访问指令间接访问VM控制结构（VMCS）。在一个实施例中，访问指令包括由处理器用于确定VMCS组件的适当存储位置的VMCS组件标识符。处理器识别处理器存储器或存储器内的VMCS组件的适当存储位置。

8. 发明授权

US07296267B2 System and method for binding virtual machines to hardware contexts 有权
标题翻译：将虚拟机绑定到硬件上下文的系统和方法
公开(公告)号：US07296267B2
公开(公告)日：2007-11-13
申请号：US10194822
申请日：2002-07-12
申请人： Erik C. Cota-Robles , Randolph L. Campbell , Clifford D. Hall , Gilbert Neiger , Richard A. Uhlig
发明人： Erik C. Cota-Robles , Randolph L. Campbell , Clifford D. Hall , Gilbert Neiger , Richard A. Uhlig
IPC分类号： G06F9/455 , G06F9/46
CPC分类号： G06F9/505 , G06F9/45533 , G06F9/5044
摘要： System and method for binding virtual machines to hardware contexts. A method includes obtaining resource requirements for a plurality of virtual machines, and binding one or more of the plurality of virtual machines to one or more of a plurality of hardware contexts associated with a processor based upon the resource requirements. The resource requirements may be the bandwidth and latency of the virtual machines. The method may be implemented as software on a storage device on a computing device having a processor that supports multiple hardware contexts. The method is particularly beneficial for real-time virtual machines.
摘要翻译：将虚拟机绑定到硬件上下文的系统和方法。一种方法包括获得多个虚拟机的资源需求，并且基于资源需求，将多个虚拟机中的一个或多个绑定到与处理器相关联的多个硬件上下文中的一个或多个。资源需求可能是虚拟机的带宽和延迟。该方法可以被实现为具有支持多个硬件上下文的处理器的计算设备上的存储设备上的软件。该方法对于实时虚拟机特别有益。

9. 发明授权

US08938737B2 Delivering interrupts directly to a virtual processor 有权
标题翻译：将中断直接传递到虚拟处理器
公开(公告)号：US08938737B2
公开(公告)日：2015-01-20
申请号：US13605412
申请日：2012-09-06
申请人： Gilbert Neiger , Rajesh Sankaran Madukkarumukumana , Richard A. Uhlig , Udo Steinberg , Sebastian Schoenberg , Sridhar Muthrasanallur , Steven M. Bennett , Andrew V. Anderson , Erik C. Cota-Robles
发明人： Gilbert Neiger , Rajesh Sankaran Madukkarumukumana , Richard A. Uhlig , Udo Steinberg , Sebastian Schoenberg , Sridhar Muthrasanallur , Steven M. Bennett , Andrew V. Anderson , Erik C. Cota-Robles
IPC分类号： G06F9/455 , G06F13/24 , G06F13/26 , G06F9/48
CPC分类号： G06F13/24 , G06F9/45533 , G06F9/4812
摘要： Embodiments of apparatuses, methods, and systems for delivering an interrupt to a virtual processor are disclosed. In one embodiment, an apparatus includes an interface to receive an interrupt request, delivery logic, and exit logic. The delivery logic is to determine, based on an attribute of the interrupt request, whether the interrupt request is to be delivered to the virtual processor. The exit logic is to transfer control to a host if the delivery logic determines that the interrupt request is not to be delivered to the virtual processor.
摘要翻译：公开了用于向虚拟处理器递送中断的装置，方法和系统的实施例。在一个实施例中，装置包括用于接收中断请求，传递逻辑和退出逻辑的接口。交付逻辑是基于中断请求的属性来确定中断请求是否被传送到虚拟处理器。如果传递逻辑确定中断请求不被传送到虚拟处理器，则出口逻辑是将控制传送到主机。

10. 发明申请

US20140053155A1 VIRTUALIZING PERFORMANCE COUNTERS 审中-公开
标题翻译：虚拟化性能计数器
公开(公告)号：US20140053155A1
公开(公告)日：2014-02-20
申请号：US14060947
申请日：2013-10-23
申请人： Erik C. Cota-Robles , Gilbert Neiger , Steven M. Bennett , Andrew V. Anderson
发明人： Erik C. Cota-Robles , Gilbert Neiger , Steven M. Bennett , Andrew V. Anderson
IPC分类号： G06F9/455
CPC分类号： G06F9/45533 , G06F9/455 , G06F9/45558 , G06F9/46 , G06F9/461 , G06F9/462 , G06F9/468 , G06F11/3409 , G06F11/3466 , G06F11/348 , G06F2009/45591 , G06F2201/815 , G06F2201/86 , G06F2201/88 , G06F2201/885
摘要： Embodiments of apparatuses, methods, and systems for virtualizing performance counters are disclosed. In one embodiment, an apparatus includes a counter, a counter enable storage location, counter enable logic, and virtual machine control logic. The counter enable storage location is to store a counter enable indicator. The counter enable logic is to enable the counter based on the counter enable indicator. The virtual machine control logic is to transfer control of the apparatus to a guest. The virtual machine control logic includes guest state load logic to cause a guest value from a virtual machine control structure to be loaded into the counter enable storage location in connection with a transfer of control of the apparatus to the guest.
摘要翻译：公开了用于虚拟化性能计数器的装置，方法和系统的实施例。在一个实施例中，装置包括计数器，计数器使能存储位置，计数器使能逻辑和虚拟机器控制逻辑。计数器使能存储位置是存储计数器使能指示符。计数器使能逻辑是基于计数器使能指示器启用计数器。虚拟机控制逻辑是将设备的控制传送给客人。虚拟机控制逻辑包括客户端状态负载逻辑，以使来自虚拟机控制结构的客户值被加载到计数器使能存储位置中，并将该设备的控制转移给客户端。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式