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1. 发明申请

US20220058469A1 SMART MEMORY HANDLING AND DATA MANAGEMENT FOR MACHINE LEARNING NETWORKS 有权
公开(公告)号：US20220058469A1
公开(公告)日：2022-02-24
申请号：US17394671
申请日：2021-08-05
申请人： Intel Corporation
发明人： TOMER SCHWARTZ , Ehud Cohen , Uzi Sarel , Amitai Armon , Yaniv Fais , Lev Faivishevsky , Amit Bleiweiss , Yahav Shadmiy , Jacob Subag
IPC分类号： G06N3/063 , G06N3/04 , G06N3/08
摘要： A mechanism is described for facilitating memory handling and data management in machine learning at autonomous machines. A method of embodiments, as described herein, includes detecting multiple tables associated with multiple neural networks at multiple autonomous machines, where each of the multiple tables include an index. The method may further include combining the multiple tables and multiple indexes associated with the multiple tables into a single table and a single index, respectively, where the single table is communicated to the multiple autonomous machines to allow simultaneous processing of one or more portions of the single table using one or more memory devices and one or more processors of one or more of the multiple autonomous machines.

2. 发明授权

US11093822B2 Variable precision and mix type representation of multiple layers in a network 有权
公开(公告)号：US11093822B2
公开(公告)日：2021-08-17
申请号：US15499896
申请日：2017-04-28
申请人： Intel Corporation
发明人： Uzi Sarel , Ehud Cohen , Tomer Schwartz , Amitai Armon , Yahav Shadmiy , Amit Bleiweiss , Gal Leibovich , Jeremie Dreyfuss , Lev Faivishevsky , Tomer Bar-On , Yaniv Fais , Jacob Subag
IPC分类号： G06N3/063 , G06F9/30 , G06N3/04 , G06N3/08
摘要： In an example, an apparatus comprises a plurality of execution units comprising at least a first type of execution unit and a second type of execution unit and logic, at least partially including hardware logic, to expose embedded cast operations in at least one of a load instruction or a store instruction; determine a target precision level for the cast operations; and load the cast operations at the target precision level. Other embodiments are also disclosed and claimed.

3. 发明申请

US20210141604A1 MULTIPLY-ACCUMULATE "0" DATA GATING 有权
公开(公告)号：US20210141604A1
公开(公告)日：2021-05-13
申请号：US17103179
申请日：2020-11-24
申请人： Intel Corporation
发明人： Yaniv Fais , Tomer Bar-On , Jacob Subag , Jeremie Dreyfuss , Lev Faivishevsky , Michael Behar , Amit Bleiweiss , Guy Jacob , Gal Leibovich , Itamar Ben-Ari , Galina Ryvchin , Eyal Yaacoby
IPC分类号： G06F7/533 , G06N20/00 , G06T1/20
摘要： In an example, an apparatus comprises a plurality of execution units and logic, at least partially including hardware logic, to gate at least one of a multiply unit or an accumulate unit in response to an input of value zero. Other embodiments are also disclosed and claimed.

4. 发明授权

US10606559B2 Multiply-accumulate “0” data gating 有权
公开(公告)号：US10606559B2
公开(公告)日：2020-03-31
申请号：US16439174
申请日：2019-06-12
申请人： INTEL CORPORATION
发明人： Yaniv Fais , Tomer Bar-On , Jacob Subag , Jeremie Dreyfuss , Lev Faivishevsky , Michael Behar , Amit Bleiweiss , Guy Jacob , Gal Leibovich , Itamar Ben-Ari , Galina Ryvchin , Eyal Yaacoby
IPC分类号： G06F7/533 , G06N20/00 , G06T1/20
摘要： In an example, an apparatus comprises a plurality of execution units and logic, at least partially including hardware logic, to gate at least one of a multiply unit or an accumulate unit in response to an input of value zero. Other embodiments are also disclosed and claimed.

5. 发明申请

US20180307982A1 REAL TIME CONTEXT DEPENDENT DEEP LEARNING 审中-公开
公开(公告)号：US20180307982A1
公开(公告)日：2018-10-25
申请号：US15494887
申请日：2017-04-24
申请人： Intel Corporation
发明人： Lev Faivishevsky , Tomer Bar-On , Yaniv Fais , Jacob Subag , Jeremie Dreyfuss , Amit Bleiweiss , Tomer Schwartz
IPC分类号： G06N3/08 , G06N99/00
CPC分类号： G06N3/08 , G06N99/005 , G06T1/20
摘要： In an example, an apparatus comprises a plurality of execution units comprising and logic, at least partially including hardware logic, to receive a plurality of data inputs for training a neural network, wherein the data inputs comprise training data and weights inputs; represent the data inputs in a first form; and represent the weight inputs in a second form. Other embodiments are also disclosed and claimed.

6. 发明授权

US09536342B2 Automatic partitioning techniques for multi-phase pixel shading 有权
标题翻译：多相像素着色自动分割技术
公开(公告)号：US09536342B2
公开(公告)日：2017-01-03
申请号：US14461047
申请日：2014-08-15
申请人： INTEL CORPORATION
发明人： Uzi Sarel , Tomer Bar-On , Jacob Subag
IPC分类号： G06T15/20 , G06T15/80 , G06T15/00 , G06F9/455
CPC分类号： G06T15/005 , G06F9/455
摘要： Automatic partitioning techniques for multi-phase pixel shading are described. In an example embodiment, an apparatus may comprise logic, at least a portion of which is in hardware, the logic to determine one or more respective suitability metrics for each of one or more candidate partitioning policies for a set of pixel shader inputs for a graphics frame, each candidate partitioning policy comprising one or more rules for partitioning the set of pixel shader inputs for multi-phase pixel shading based on quality sensitivity values for the pixel shader inputs, select a partitioning policy for the set of pixel shader inputs from among the one or more candidate partitioning policies based on the determined suitability metrics, and construct a multi-phase pixel shader for the graphics frame by partitioning the set of pixel shader inputs into multiple classes according to the selected partitioning policy. Other embodiments are described and claimed.
摘要翻译：描述了多相像素着色的自动划分技术。在示例实施例中，装置可以包括其硬件中的至少一部分的逻辑，用于为图形的一组像素着色器输入确定一个或多个候选分区策略中的每一个的一个或多个相应的适合性度量的逻辑帧，每个候选分区策略包括用于基于用于像素着色器输入的质量敏感度值来分割用于多相位像素着色的多个像素着色器输入的集合的一个或多个规则，从所述像素着色器输入的集合中选择所述像素着色器输入的分区策略基于所确定的适合性度量的一个或多个候选分区策略，并且根据所选择的分区策略，将所述像素着色器输入集合划分为多个类，从而构建用于所述图形帧的多相像素着色器。描述和要求保护其他实施例。

7. 发明申请

US20220237850A1 SUB-GRAPH IN FREQUENCY DOMAIN AND DYNAMIC SELECTION OF CONVOLUTION IMPLEMENTATION ON A GPU 有权
公开(公告)号：US20220237850A1
公开(公告)日：2022-07-28
申请号：US17669126
申请日：2022-02-10
申请人： Intel Corporation
发明人： Uzi Sarel , Ehud Cohen , Tomer Schwartz , Amitai Armon , Yahav Shadmiy , Itamar Ben-Ari , Amit Bleiweiss , Lev Faivishevsky , Tomer Bar-On , Yaniv Fais , Jacob Subag , Michael Behar , Guy Jacob , Gal Leibovich , Jeremie Dreyfuss
IPC分类号： G06T15/00 , G06N3/02 , G06N3/04 , G06N3/063 , G06N3/08
摘要： In an example, an apparatus comprises a plurality of execution units; and logic, at least partially including hardware logic, to determine a sub-graph of a network that can be executed in a frequency domain and apply computations in the sub-graph in the frequency domain. Other embodiments are also disclosed and claimed.

8. 发明申请

US20220076118A1 REAL TIME CONTEXT DEPENDENT DEEP LEARNING 有权
公开(公告)号：US20220076118A1
公开(公告)日：2022-03-10
申请号：US17404153
申请日：2021-08-17
申请人： Intel Corporation
发明人： Lev Faivishevsky , Tomer Bar-On , Yaniv Fais , Jacob Subag , Jeremie Dreyfuss , Amit Bleiweiss , Tomer Schwartz , Raanan Yonatan Yehezkel Rohekar , Michael Behar , Amitai Armon , Uzi Sarel
IPC分类号： G06N3/08 , G06N20/10 , G06N20/00
摘要： In an example, an apparatus comprises a plurality of execution units comprising and logic, at least partially including hardware logic, to receive a plurality of data inputs for training a neural network, wherein the data inputs comprise training data and weights inputs; represent the data inputs in a first form; and represent the weight inputs in a second form. Other embodiments are also disclosed and claimed.

9. 发明授权

US11087206B2 Smart memory handling and data management for machine learning networks 有权
公开(公告)号：US11087206B2
公开(公告)日：2021-08-10
申请号：US15581045
申请日：2017-04-28
申请人： Intel Corporation
发明人： Tomer Schwartz , Ehud Cohen , Uzi Sarel , Amitai Armon , Yaniv Fais , Lev Faivishevsky , Amit Bleiweiss , Yahav Shadmiy , Jacob Subag
IPC分类号： G06N3/063 , G06N3/04 , G06N3/08
摘要： A mechanism is described for facilitating memory handling and data management in machine learning at autonomous machines. A method of embodiments, as described herein, includes detecting multiple tables associated with multiple neural networks at multiple autonomous machines, where each of the multiple tables include an index. The method may further include combining the multiple tables and multiple indexes associated with the multiple tables into a single table and a single index, respectively, where the single table is communicated to the multiple autonomous machines to allow simultaneous processing of one or more portions of the single table using one or more memory devices and one or more processors of one or more of the multiple autonomous machines.

10. 发明授权

US10559112B2 Hybrid mechanism for efficient rendering of graphics images in computing environments 有权
公开(公告)号：US10559112B2
公开(公告)日：2020-02-11
申请号：US15179678
申请日：2016-06-10
申请人： INTEL CORPORATION
发明人： Tatiana Surazhsky , Uzi Sarel , Jacob Subag
IPC分类号： G06T15/00
摘要： A mechanism is described for facilitating hybrid rendering of graphics images in computing environments. A method of embodiments, as described herein, includes detecting the video stream including two-dimensional (2D) images, where the video stream is processed through a graphics pipeline at a computing device. The method may further include performing hybrid combination of a luma (Y)-plane with chrominance (UV)-planes to directly generate a YUV texture, wherein the YUV texture is used to generate three-dimensional (3D) images corresponding to the 2D images.

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