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1. 发明授权

US08101476B2 Stress memorization dielectric optimized for NMOS and PMOS 有权
标题翻译：针对NMOS和PMOS优化的应力记忆电介质
公开(公告)号：US08101476B2
公开(公告)日：2012-01-24
申请号：US12541335
申请日：2009-08-14
申请人： Kanan Garg , Haowen Bu , Mahalingam Nandakumar , Song Zhao
发明人： Kanan Garg , Haowen Bu , Mahalingam Nandakumar , Song Zhao
IPC分类号： H01L21/8238
CPC分类号： H01L21/823842 , H01L21/3185 , H01L21/823807 , H01L29/7843 , H01L29/7845
摘要： A method for forming a tensile SiN stress layer for stress memorization enhancement of NMOS transistors with a high Si—H/N—H bond ratio that does not degrade PMOS transistors. A CMOS integrated circuit is processed through a NMOS source and drain implant but not through NMOS source and drain anneal. A SiN dielectric layer is deposited such that an area ratio of a Si—H peak to a N—H peak in a FTIR spectrum is greater than 7 and a tensile stress of the SiN dielectric is greater than 150 MPa. The CMOS integrated circuit is annealed after deposition of the SiN dielectric layer and the SiN dielectric layer is removed from at least a part of the integrated circuit.
摘要翻译：一种用于形成具有不降低PMOS晶体管的高Si-H / N-H键比的NMOS晶体管的应力记忆增强的拉伸SiN应力层的方法。 CMOS集成电路通过NMOS源极和漏极注入而不是通过NMOS源极和漏极退火进行处理。沉积SiN电介质层，使得FTIR光谱中Si-H峰与N-H峰的面积比大于7，并且SiN电介质的拉伸应力大于150MPa。在沉积SiN电介质层之后对CMOS集成电路进行退火，并且从集成电路的至少一部分去除SiN介电层。

2. 发明申请

US20060024873A1 Method of incorporating stress into a transistor channel by use of a backside layer 有权
标题翻译：通过使用背面层将应力引入晶体管沟道的方法
公开(公告)号：US20060024873A1
公开(公告)日：2006-02-02
申请号：US10902657
申请日：2004-07-28
申请人： Mahalingam Nandakumar , Haowen Bu
发明人： Mahalingam Nandakumar , Haowen Bu
IPC分类号： H01L21/336 , H01L21/8234
CPC分类号： H01L29/7833 , H01L21/823807 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7843
摘要： The present invention provides the method includes forming source/drain regions 170 in a semiconductor wafer substrate 110 adjacent a gate structure 130 located on a front side of the semiconductor wafer substrate 110. The source/drain regions 170 have a channel region 175 located between them. A first stress-inducing layer 190 is placed on a backside of the semiconductor wafer substrate 110 and is subjected to a thermal anneal to cause a stress to form in the channel region 175.
摘要翻译：本发明提供的方法包括在位于半导体晶片衬底110的前侧的栅极结构130附近的半导体晶片衬底110中形成源/漏区170。源极/漏极区170具有位于它们之间的沟道区175。第一应力诱导层190放置在半导体晶片衬底110的背面，并进行热退火以在沟道区175中形成应力。

3. 发明申请

US20050118770A1 Method for introducing hydrogen into a channel region of a metal oxide semiconductor (MOS) device 审中-公开
标题翻译：将氢引入金属氧化物半导体（MOS）器件的沟道区域的方法
公开(公告)号：US20050118770A1
公开(公告)日：2005-06-02
申请号：US10956864
申请日：2004-10-01
申请人： Mahalingam Nandakumar , Shaoping Tang , Haowen Bu
发明人： Mahalingam Nandakumar , Shaoping Tang , Haowen Bu
IPC分类号： H01L21/30 , H01L21/324 , H01L21/336 , H01L29/78 , H01L29/94
CPC分类号： H01L29/6659 , H01L21/3003 , H01L21/324 , H01L29/665 , H01L29/6656 , H01L29/7833 , H01L29/7842 , H01L29/7843
摘要： The present invention provides a method for manufacturing a semiconductor device and a method for manufacturing an integrated circuit including the same. The method for manufacturing the semiconductor device, among other steps, includes forming a gate structure (230) over a substrate (210) and forming at least a portion of source/drain regions in the substrate (210). The method further includes annealing the substrate containing the at least a portion of source/drain regions in the presence of hydrogen, and forming an interlevel dielectric layer over the substrate (210) having previously been annealed in the presence of hydrogen.
摘要翻译：本发明提供一种半导体器件的制造方法及其制造方法。除了其他步骤之外，制造半导体器件的方法包括在衬底（210）上形成栅极结构（230）并且形成衬底（210）中的源极/漏极区域的至少一部分。该方法还包括在存在氢的情况下对包含至少一部分源极/漏极区的衬底进行退火，以及在预先在氢气存在下预先退火的衬底（210）上形成层间电介质层。

4. 发明授权

US07402535B2 Method of incorporating stress into a transistor channel by use of a backside layer 有权
标题翻译：通过使用背面层将应力引入晶体管沟道的方法
公开(公告)号：US07402535B2
公开(公告)日：2008-07-22
申请号：US10902657
申请日：2004-07-28
申请人： Mahalingam Nandakumar , Haowen Bu
发明人： Mahalingam Nandakumar , Haowen Bu
IPC分类号： H01L21/469 , H01L21/31
CPC分类号： H01L29/7833 , H01L21/823807 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7843
摘要： The present invention provides the method includes forming source/drain regions 170 in a semiconductor wafer substrate 110 adjacent a gate structure 130 located on a front side of the semiconductor wafer substrate 110. The source/drain regions 170 have a channel region 175 located between them. A first stress-inducing layer 190 is placed on a backside of the semiconductor wafer substrate 110 and is subjected to a thermal anneal to cause a stress to form in the channel region 175.
摘要翻译：本发明提供的方法包括在位于半导体晶片衬底110的前侧的栅极结构130附近的半导体晶片衬底110中形成源/漏区170。源极/漏极区170具有位于它们之间的沟道区175。第一应力诱导层190放置在半导体晶片衬底110的背面，并进行热退火以在沟道区175中形成应力。

5. 发明申请

US20090309140A1 IN-SITU CARBON DOPED e-SiGeCB STACK FOR MOS TRANSISTOR 有权
标题翻译：用于MOS晶体管的In-SITU碳掺杂e-SiGeCB堆叠
公开(公告)号：US20090309140A1
公开(公告)日：2009-12-17
申请号：US12482896
申请日：2009-06-11
申请人： Rajesh B. Khamankar , Haowen Bu , Douglas Tad Grider
发明人： Rajesh B. Khamankar , Haowen Bu , Douglas Tad Grider
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/0847 , H01L21/823418 , H01L21/823814 , H01L29/165 , H01L29/66636 , H01L29/7833
摘要： An integrated circuit containing a PMOS transistor with p-channel source/drain (PSD) regions which include a three layer PSD stack containing Si—Ge, carbon and boron. The first PSD layer is Si—Ge and includes carbon at a density between 5×1019 and 2×1020 atoms/cm3. The second PSD layer is Si—Ge and includes carbon at a density between 5'31019 atoms/cm3 and 2×1020 atoms/cm3 and boron at a density above 5×1019 atoms/cm3. The third PSD layer is silicon or Si—Ge, includes boron at a density above 5×1019 atoms/cm3 and is substantially free of carbon. After formation of the three layer epitaxial stack, the first PSD layer has a boron density less than 10 percent of the boron density in the second PSD layer. A process for forming an integrated circuit containing a PMOS transistor with a three layer PSD stack in PSD recesses.
摘要翻译：包含具有p沟道源极/漏极（PSD）区域的PMOS晶体管的集成电路，其包括含有Si-Ge，碳和硼的三层PSD堆叠。第一PSD层是Si-Ge，并且包括密度在5×1019到2×1020原子/ cm3之间的碳。第二PSD层是Si-Ge，并且包括密度在5×1019原子/ cm3至2×1020原子/ cm3之间的碳和密度高于5×1019原子/ cm3的硼。第三PSD层是硅或Si-Ge，包括密度高于5×1019原子/ cm3的硼并且基本上不含碳。在形成三层外延堆叠之后，第一PSD层的硼密度小于第二PSD层中硼密度的10％。一种在PSD凹槽中形成具有三层PSD堆叠的PMOS晶体管的集成电路的工艺。

6. 发明授权

US07601575B2 Integration of pre-S/D anneal selective nitride/oxide composite cap for improving transistor performance 有权
标题翻译：用于改善晶体管性能的前S / D退火选择性氮化物/氧化物复合帽的集成
公开(公告)号：US07601575B2
公开(公告)日：2009-10-13
申请号：US11072779
申请日：2005-03-04
申请人： Haowen Bu , Shashank Ekbote , Rajesh Khamankar , Shaoping Tang , Freidoon Mehrad
发明人： Haowen Bu , Shashank Ekbote , Rajesh Khamankar , Shaoping Tang , Freidoon Mehrad
IPC分类号： H01L21/336 , H01L21/8234 , H01L21/44
CPC分类号： H01L29/0847 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7833 , H01L29/7845 , Y10S438/902
摘要： The present invention facilitates semiconductor device operation and fabrication by providing a cap-annealing process that improves channel electron mobility without substantially degrading PMOS transistor devices. The process uses an oxide/nitride composite cap to alter the active dopant profile across the channel regions. During an annealing process, dopants migrate out of the Si/SiO2 in a channel region thereby altering the dopant profile of the channel region. This altered profile generally improves channel mobility thereby improving transistor performance and permitting smaller density designs.
摘要翻译：本发明通过提供一种提高沟道电子迁移率而不会使PMOS晶体管器件基本上衰减的帽退火工艺来促进半导体器件的操作和制造。该方法使用氧化物/氮化物复合帽来改变通道区域上的活性掺杂剂分布。在退火过程中，掺杂剂在沟道区中迁移出Si / SiO 2，从而改变沟道区的掺杂物分布。这种改变的形状通常改善了沟道迁移率，从而提高了晶体管的性能并允许更小的密度设计。

7. 发明申请

US20070218662A1 Antimony ion implantation for semiconductor components 有权
标题翻译：半导体元件的锑离子注入
公开(公告)号：US20070218662A1
公开(公告)日：2007-09-20
申请号：US11725927
申请日：2007-03-20
申请人： Haowen Bu , Amitabh Jain , Srinivasan Chakravarthi , Shashank Ekbote
发明人： Haowen Bu , Amitabh Jain , Srinivasan Chakravarthi , Shashank Ekbote
IPC分类号： H01L21/425
CPC分类号： H01L29/6659 , H01L21/26506 , H01L21/26513 , H01L21/26586 , H01L21/324 , H01L29/6653 , H01L29/7833
摘要： A method is disclosed for implanting and activating antimony as a dopant in a semiconductor substrate. A method is also disclosed for implanting and activating antimony to form a source/drain extension region in the formation of a transistor, in such a manner as to achieve high activation and avoid deactivation via subsequent exposure to high temperatures. This technique facilitates the formation of very thin source/drain regions that exhibit reduced sheet resistance while also suppressing short channel effects. Enhancements to these techniques are also suggested for more precise implantation of antimony to create a shallower source/drain extension, and to ensure formation of the source/drain extension region to underlap the gate. Also disclosed are transistors and other semiconductor components that include doped regions comprising activated antimony, such as those formed according to the disclosed methods.
摘要翻译：公开了一种用于在半导体衬底中注入和活化锑作为掺杂剂的方法。还公开了一种用于注入和活化锑以形成晶体管的源极/漏极延伸区域的方法，以便实现高激活并避免随后暴露于高温而失活。该技术有助于形成非常薄的源极/漏极区域，其表现出降低的薄层电阻，同时还抑制短沟道效应。还建议对这些技术的增强用于更精确地注入锑以产生较浅的源极/漏极延伸，并且确保形成源极/漏极延伸区域以使栅极下沉。还公开了晶体管和其它半导体组件，其包括包含活性锑的掺杂区域，例如根据所公开的方法形成的那些。

8. 发明授权

US07253049B2 Method for fabricating dual work function metal gates 有权
标题翻译：双功能金属门制造方法
公开(公告)号：US07253049B2
公开(公告)日：2007-08-07
申请号：US11017469
申请日：2004-12-20
申请人： Jiong-Ping Lu , Shaofeng Yu , Haowen Bu , Lindsey H. Hall , Mark R. Visokay
发明人： Jiong-Ping Lu , Shaofeng Yu , Haowen Bu , Lindsey H. Hall , Mark R. Visokay
IPC分类号： H01L21/8238
CPC分类号： H01L21/823842 , H01L21/28097 , H01L21/28518 , H01L29/4975 , H01L29/51 , H01L29/6659 , H01L29/7833
摘要： A method for making PMOS and NMOS transistors 60, 70 on a semiconductor substrate 20 that includes having a gate protection layer 210 over the gate electrode layer 110 during the formation of source/drain silicides 120. The method may include implanting dopants into a gate polysilicon layer 115 before forming the protection layer 215.
摘要翻译：一种用于在半导体衬底20上制造PMOS和NMOS晶体管60,70的方法，其包括在源/漏硅化物120形成期间在栅电极层110上方具有栅极保护层210。该方法可以包括在形成保护层215之前将掺杂剂注入到栅极多晶硅层115中。

9. 发明授权

US07244654B2 Drive current improvement from recessed SiGe incorporation close to gate 有权
标题翻译：驱动目前从嵌入式SiGe并入门口的改进
公开(公告)号：US07244654B2
公开(公告)日：2007-07-17
申请号：US10901568
申请日：2004-07-29
申请人： Pr Chidambaram , Douglas T. Grider , Brian A. Smith , Haowen Bu , Lindsey Hall
发明人： Pr Chidambaram , Douglas T. Grider , Brian A. Smith , Haowen Bu , Lindsey Hall
IPC分类号： H01L21/336
CPC分类号： H01L29/6659 , H01L21/823807 , H01L21/823814 , H01L29/665 , H01L29/6656 , H01L29/66636 , H01L29/7842 , H01L29/7848
摘要： A method (100) of forming a transistor includes forming a gate structure (106, 108) over a semiconductor body and forming recesses (112) substantially aligned to the gate structure in the semiconductor body. Silicon germanium is then epitaxially grown (114) in the recesses, followed by forming sidewall spacers (118) over lateral edges of the gate structure. The method continues by implanting source and drain regions in the semiconductor body (120) after forming the sidewall spacers. The silicon germanium formed in the recesses resides close to the transistor channel and serves to provide a compressive stress to the channel, thereby facilitating improved carrier mobility in PMOS type transistor devices.
摘要翻译：形成晶体管的方法（100）包括在半导体主体上形成栅极结构（106,108），并形成与半导体本体中的栅极结构基本对齐的凹槽（112）。然后在凹槽中外延生长硅（114），随后在栅极结构的横向边缘上形成侧壁间隔物（118）。该方法通过在形成侧壁间隔物之后将源区和漏区注入半导体本体（120）中来继续。在凹槽中形成的硅锗位于晶体管沟道附近，用于向通道提供压缩应力，从而有助于改善PMOS型晶体管器件的载流子迁移率。

10. 发明申请

US20070105368A1 Method of fabricating a microelectronic device using electron beam treatment to induce stress 审中-公开
标题翻译：使用电子束处理制造微电子器件以诱导应力的方法
公开(公告)号：US20070105368A1
公开(公告)日：2007-05-10
申请号：US11268036
申请日：2005-11-07
申请人： Ting Tsui , Andrew McKerrow , Haowen Bu , Robert Kraft
发明人： Ting Tsui , Andrew McKerrow , Haowen Bu , Robert Kraft
IPC分类号： H01L21/469
CPC分类号： H01L21/823807 , H01L21/3105 , H01L21/3148 , H01L21/3185 , H01L21/823864
摘要： The present invention, in one embodiment, provides a method of fabricating a microelectronics device 200. This embodiment comprises forming a liner 310 over a substrate 210 and a gate structure 230, subjecting the liner 310 to an electron beam 405 and depositing a pre-metal dielectric layer 415 over the liner 310.
摘要翻译：本发明在一个实施例中提供了一种制造微电子器件200的方法。该实施例包括在衬底210和栅极结构230上形成衬垫310，使衬垫310经受电子束405并在衬垫310上沉积预金属介电层415。

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