专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06404375B1 System and method of selecting and using bit testing sequences during successive approximation for calibrating an analog-to-digital converter 失效
标题翻译：在逐次逼近期间选择和使用位测试序列以校准模数转换器的系统和方法
公开(公告)号：US06404375B1
公开(公告)日：2002-06-11
申请号：US09393091
申请日：1999-09-09
申请人： Carlos Esteban Muñoz , Karl Ernesto Thompson , Douglas S. Piasecki , Wai Laing Lee , Eric Swanson
发明人： Carlos Esteban Muñoz , Karl Ernesto Thompson , Douglas S. Piasecki , Wai Laing Lee , Eric Swanson
IPC分类号： H03M112
CPC分类号： H03M1/1042 , H03M1/0692 , H03M1/109 , H03M1/46
摘要： A digital calibration system for an analog-to-digital converter system includes a computational system receiving digital bits from an analog-to-digital converter representing selection of elements of the digital-to-analog converter in response to an analog input. The computational engine produces a digital output representative of the analog input during conversion operation, and digital values for adjustment of an adjustable analog source during calibration. Further, a digital system comprises a radix-less-than-two non-configurable digital-to-analog converter, a comparator system connected to the converter, and a computational system configured for SAR calibration and conversion.
摘要翻译：用于模数转换器系统的数字校准系统包括计算系统，其接收来自模数转换器的数字位，其响应于模拟输入来表示选择数模转换器的元件。计算引擎在转换操作期间产生代表模拟输入的数字输出，以及用于在校准期间调节可调模拟源的数字值。此外，数字系统包括二进制以下的不可配置的数模转换器，连接到转换器的比较器系统以及被配置用于SAR校准和转换的计算系统。

2. 发明授权

US06252454B1 Calibrated quasi-autozeroed comparator systems and methods 有权
标题翻译：校准的准自动比较系统和方法
公开(公告)号：US06252454B1
公开(公告)日：2001-06-26
申请号：US09393055
申请日：1999-09-09
申请人： Karl Ernesto Thompson , Carlos Esteban Muñoz , Douglas S. Piasecki , Wai Laing Lee , Eric Swanson
发明人： Karl Ernesto Thompson , Carlos Esteban Muñoz , Douglas S. Piasecki , Wai Laing Lee , Eric Swanson
IPC分类号： H03F102
CPC分类号： H03F3/45986 , H03F1/0233
摘要： A multistage comparator is calibrated to remove quasi-autozero voltages derived from the native comparator offset and autozero switch charge injection offsets. A multistage comparator includes a plurality of series connected amplifiers each having a programmable source, and further including a latch. A calibration method for a multistage comparator includes calibrating the first of a series of amplifiers first for both voltage offset and charge injection errors thereby to remove the quasi-autozero voltage and charge injection offsets.
摘要翻译：校准多级比较器以消除由本机比较器偏移和自动调零开关电荷注入偏移导出的准自动调零电压。多级比较器包括多个串联连接的放大器，每个具有可编程源，并且还包括锁存器。用于多级比较器的校准方法包括首先校准电压偏移和电荷注入误差的一系列放大器中的第一个，从而去除准自动零电压和电荷注入偏移。

3. 发明授权

US06486806B1 Systems and methods for adaptive auto-calibration of Radix<2 A/D SAR converters with internally generated stimuli 有权
标题翻译：具有内部产生刺激的Radix <2 A / D SAR转换器的自适应自动校准系统和方法
公开(公告)号：US06486806B1
公开(公告)日：2002-11-26
申请号：US09393828
申请日：1999-09-09
申请人： Carlos Esteban Muñoz , Karl Ernesto Thompson , Douglas S. Piasecki , Wai Laing Lee , Eric Swanson
发明人： Carlos Esteban Muñoz , Karl Ernesto Thompson , Douglas S. Piasecki , Wai Laing Lee , Eric Swanson
IPC分类号： H03M110
CPC分类号： H03M1/1038 , H03M1/0692 , H03M1/468 , H03M1/804
摘要： An auto-calibrating companion bit successive approximation system uses sampling and balancing capacitors in a charge redistribution digital-to-analog converter having multi-valued capacitors of magnitudes enabling redundant expression of electric charge values. Companion bits are used with sets of balancing capacitors for successive approximation of sampling voltages. A charge redistribution digital-to-analog converter has a sampling and balancing capacitors including associated companion bit capacitors represented by digital weights which are saved in memory. A non-binary weighted set of capacitors provides redundancy in a charge redistribution digital-to-analog converter employed in a successive approximation register architecture.
摘要翻译：自动校准伴随位逐次逼近系统使用电荷再分配数模转换器中的采样和平衡电容器，其具有能够实现电荷值的冗余表达的具有多值电容器的多值电容器。伴随位用于平衡电容器组，用于逐次逼近采样电压。电荷再分配数模转换器具有采样和平衡电容器，其包括被保存在存储器中的由数字权重表示的相关伴随位电容器。非二进制加权电容集合在逐次逼近寄存器架构中采用的电荷再分配数模转换器中提供冗余。

4. 发明授权

US06424276B1 Successive approximation algorithm-based architectures and systems 失效
标题翻译：基于连续近似算法的架构和系统
公开(公告)号：US06424276B1
公开(公告)日：2002-07-23
申请号：US09393093
申请日：1999-09-09
申请人： Carlos Esteban Muñoz , Karl Ernesto Thompson , Douglas S. Piasecki , Wai Laing Lee , Eric Swanson
发明人： Carlos Esteban Muñoz , Karl Ernesto Thompson , Douglas S. Piasecki , Wai Laing Lee , Eric Swanson
IPC分类号： H03M110
CPC分类号： H03M1/1061 , H03M1/0692 , H03M1/46 , H03M1/804
摘要： A digital calibration system for an analog-to-digital converter system includes a computational system receiving digital bits from an analog-to-digital converter representing selection of elements of the digital-to-analog converter in response to an analog input. The computational engine produces a digital output representative of the analog input during conversion operation, and digital values for adjustment of an adjustable analog source during calibration. Further, a digital system comprises a radix-less-than-two non-configurable digital-to-analog converter, a comparator system connected to the converter, and a computational system configured for SAR calibration and conversion.
摘要翻译：用于模数转换器系统的数字校准系统包括计算系统，其接收来自模数转换器的数字位，其响应于模拟输入来表示选择数模转换器的元件。计算引擎在转换操作期间产生代表模拟输入的数字输出，以及用于在校准期间调节可调模拟源的数字值。此外，数字系统包括二进制以下的不可配置的数模转换器，连接到转换器的比较器系统以及被配置用于SAR校准和转换的计算系统。

5. 发明授权

US06417794B1 System and apparatus for digitally calibrating capacitors in an analog-to-digital converter using successive approximation 有权
标题翻译：用于使用逐次逼近在模数转换器中数字校准电容器的系统和装置
公开(公告)号：US06417794B1
公开(公告)日：2002-07-09
申请号：US09393826
申请日：1999-09-09
申请人： Carlos Esteban Muñoz , Karl Ernesto Thompson , Douglas S. Piasecki , Wai Laing Lee , Eric Swanson
发明人： Carlos Esteban Muñoz , Karl Ernesto Thompson , Douglas S. Piasecki , Wai Laing Lee , Eric Swanson
IPC分类号： H03M138
CPC分类号： H03M1/1061 , H03M1/0692 , H03M1/46 , H03M1/804
摘要： A digital calibration system for an analog-to-digital converter system includes a computational system receiving digital bits from an analog-to-digital converter representing selection of elements of the digital-to-analog converter in response to an analog input. The computational engine produces a digital output representative of the analog input during conversion operation, and digital values for adjustment of an adjustable analog source during calibration. Further, a digital system comprises a radix-less-than-two non-configurable digital-to-analog converter, a comparator system connected to the converter, and a computational system configured for SAR calibration and conversion.
摘要翻译：用于模数转换器系统的数字校准系统包括计算系统，其接收来自模数转换器的数字位，其响应于模拟输入来表示选择数模转换器的元件。计算引擎在转换操作期间产生代表模拟输入的数字输出，以及用于在校准期间调节可调模拟源的数字值。此外，数字系统包括二进制以下的不可配置的数模转换器，连接到转换器的比较器系统以及被配置用于SAR校准和转换的计算系统。

6. 发明授权

US06348885B1 System and method for digitally calibrating an analog-to-digital converter 失效
标题翻译：用于数字校准模拟 - 数字转换器的系统和方法
公开(公告)号：US06348885B1
公开(公告)日：2002-02-19
申请号：US09393046
申请日：1999-09-09
申请人： Carlos Estaban Muñoz , Karl Ernesto Thompson , Douglas S. Piasecki , Wai Laing Lee , Eric Swanson
发明人： Carlos Estaban Muñoz , Karl Ernesto Thompson , Douglas S. Piasecki , Wai Laing Lee , Eric Swanson
IPC分类号： H03M110
CPC分类号： H03M1/0692 , H03M1/1038 , H03M1/46 , H03M1/804
摘要： A digital calibration system for an analog-to-digital converter system includes a computational system receiving digital bits from an analog-to-digital converter representing selection of elements of the digital-to-analog converter in response to an analog input. The computational engine produces a digital output representative of the analog input during conversion operation, and digital values for adjustment of an adjustable analog source during calibration. Further, a digital system comprises a radix-less-than-two non-configurable digital-to-analog converter, a comparator system connected to the converter, and a computational system configured for SAR calibration and conversion.
摘要翻译：用于模数转换器系统的数字校准系统包括计算系统，其接收来自模数转换器的数字位，其响应于模拟输入来表示选择数模转换器的元件。计算引擎在转换操作期间产生代表模拟输入的数字输出，以及用于在校准期间调节可调模拟源的数字值。此外，数字系统包括二进制以下的不可配置的数模转换器，连接到转换器的比较器系统以及被配置用于SAR校准和转换的计算系统。

7. 发明授权

US06456220B1 Analog-to-digital converter for processing differential and single-ended inputs 有权
标题翻译：用于处理差分和单端输入的模数转换器
公开(公告)号：US06456220B1
公开(公告)日：2002-09-24
申请号：US09595959
申请日：2000-06-19
申请人： Ka Y. Leung , Douglas S. Piasecki
发明人： Ka Y. Leung , Douglas S. Piasecki
IPC分类号： H03M112
CPC分类号： H03M1/129 , H03M1/46
摘要： An analog-to-digital converter configurable for converting both differential and single-ended analog signals. Charge sharing between two input capacitors and a DAC capacitor allow the full dynamic range of the ADC device to be used when full scale differential analog input signals are converted. When configured for single-ended operation, charge sharing of the half scale single-ended input analog voltage occurs between one input capacitor and the DAC capacitor to allow the full dynamic range of the ADC device to again be utilized.
摘要翻译：可配置用于转换差分和单端模拟信号的模数转换器。两个输入电容和DAC电容之间的电荷共享允许在转换满量程差分模拟输入信号时使用ADC器件的全部动态范围。当配置为单端操作时，半标准单端输入模拟电压的电荷共享发生在一个输入电容和DAC电容之间，以允许再次使用ADC器件的完整动态范围。

8. 发明授权

US5172115A Ratiometric A/D converter with non-rationometric error offset 失效
标题翻译：具有非比例误差偏移的比例A / D转换器
公开(公告)号：US5172115A
公开(公告)日：1992-12-15
申请号：US717981
申请日：1991-06-21
申请人： Donald A. Kerth , Douglas S. Piasecki
发明人： Donald A. Kerth , Douglas S. Piasecki
IPC分类号： H03M1/10 , G01D3/00 , H03M1/06 , H03M1/12 , H03M3/00 , H03M3/02
CPC分类号： H03M1/0621 , G01D3/00 , H03M3/324 , H03M1/1019 , H03M1/12 , H03M3/382 , H03M3/458
摘要： A ratiometric converter is provided that is comprised of a dual converter system utilizing a first converter (36) and a second converter (38). The second converter (38) is operable to receive the input voltage from a load cell (10) on sense lines (12) and (14) and compare them with an internal reference. Similarly, the first A/D converter (36) is operable to receive the reference voltage to the load cell (10) and compare it with the internal reference. The output of each of the converters (36) and (38) is then input to subtraction circuits (78) and (84), respectively, in the digital domain. In a calibration mode, switches (72) and (73) shorts the reference nodes in the load cell (10) together to determine the non-ratiometric offsets., These offsets are then stored in registers (80) and (86) for the reference voltage and the input voltage, respectively. During operation, the offsets are then input to the subtraction blocks (78) and 84) and a digital subtraction performed on the output of both converters (36) and (38). The output of the subtraction blocks (78) and (84) are then input to a ratiometric operator block (52) to perform a digital division thereon. This results in a ratiometric output that has the non-ratiometric offsets removed. Thereafter, the signal is input to a system calibration block (32) to remove ratiometric errors.
摘要翻译：提供了一种比例转换器，其包括利用第一转换器（36）和第二转换器（38）的双转换器系统。第二转换器（38）可操作以从感测线路（12）和（14）上的测力传感器（10）接收输入电压，并将其与内部参考值进行比较。类似地，第一A / D转换器（36）可操作以将负载传感器（10）的参考电压接收并与内部参考值进行比较。然后，转换器（36）和（38）中的每一个的输出分别输入到数字域中的减法电路（78）和（84）。在校准模式中，开关（72）和（73）将测力传感器（10）中的参考节点一起缩短以确定非比例偏移量，然后将这些偏移量存储在寄存器（80）和（86）中，用于参考电压和输入电压。在操作期间，偏移量被输入到减法块（78）和84），并且对两个转换器（36）和（38）的输出进行数字减法。然后将减法块（78）和（84）的输出输入到比例计算器程序块（52）以对其进行数字分频。这导致具有非比例偏移量的比例输出。此后，该信号被输入到系统校准块（32）以消除比例误差。

9. 发明授权

US4945262A Voltage limiter apparatus with inherent level shifting employing MOSFETs 失效
标题翻译：具有采用MOSFET的固有电平转换的电压限制器
公开(公告)号：US4945262A
公开(公告)日：1990-07-31
申请号：US301926
申请日：1989-01-26
申请人： Douglas S. Piasecki
发明人： Douglas S. Piasecki
IPC分类号： H03K3/3565 , H03K5/00 , H03K5/13 , H03K19/003
CPC分类号： H03K19/00384 , H03K3/3565 , H03K5/133 , H03K2005/0013 , H03K2005/00195
摘要： A voltage limiter includes a first FET of a given polarity having the source electrode adapted to be connected to a positive supply terminal. There is a second FET of an opposite polarity to said first and having the source electrode adapted to be connected to a supply terminal which is negative with respect to said positive terminal. The voltage at each terminal may typically vary during operation. There is a voltage clamp means connected between the drain electrodes of said first and second FETs with the gate electrode of the first FET connected to the drain electrode of the second FET and with the gate electrode of the second FET connected to the drain electrode of the first FET, to cause the voltage across said voltage clamping means to remain constant in spite of variations in said positive and negative supplies. The voltage across the drain electrodes of the FETs is further employed as a biasing source for additional logic circuits. An output logic inverter operating with the logic circuits always has its switch point accurately defined with respect to the voltage limiting apparatus. Due to the constant voltage difference provided by the voltage limiter, the propagation delay through the logic circuits is constant with the output inverter having a controlled switching point.
摘要翻译：电压限制器包括具有给定极性的第一FET，源极电极适于连接到正电源端子。存在与所述第一FET相反极性的第二FET，并且源极适于连接到相对于所述正极端子的负极的供电端子。每个终端处的电压通常可在操作期间变化。连接在所述第一和第二FET的漏电极之间的电压钳位装置，其中第一FET的栅电极连接到第二FET的漏电极，第二FET的栅电极连接到第二FET的漏电极第一FET，以使所述电压钳位装置两端的电压保持恒定，尽管所述正电源和负电源的变化。进一步使用FET的漏电极两端的电压作为附加逻辑电路的偏置源。与逻辑电路一起工作的输出逻辑逆变器总是将其切换点相对于电压限制装置精确地定义。由于由限压器提供的恒定电压差，通过逻辑电路的传播延迟是恒定的，输出反相器具有受控的切换点。

10. 依法登记的发明

USH497H Ratioed power on reset circuit 失效
标题翻译：比率上电复位电路
公开(公告)号：USH497H
公开(公告)日：1988-07-05
申请号：US3170
申请日：1987-01-14
申请人： Douglas S. Piasecki
发明人： Douglas S. Piasecki
IPC分类号： H03K17/22
CPC分类号： H03K17/223
摘要： A ratioed power on reset apparatus utilizing two pairs of field effect transistors as voltage dividers to generate a power on reset signal which tracks the waveshape of an applied power signal with a slot rise time.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式