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1. 发明授权

US08248860B2 Memory device using a variable resistive element 有权
标题翻译：使用可变电阻元件的存储器件
公开(公告)号：US08248860B2
公开(公告)日：2012-08-21
申请号：US12659840
申请日：2010-03-23
申请人： Kwang-Jin Lee , Chang-Soo Lee , Joon-Min Park , Hui-Kwon Seo , Qi Wang
发明人： Kwang-Jin Lee , Chang-Soo Lee , Joon-Min Park , Hui-Kwon Seo , Qi Wang
IPC分类号： G11C16/04
CPC分类号： G11C13/0097 , G11C13/0004 , G11C13/0069 , G11C2013/0088 , G11C2211/5646
摘要： A memory device includes a memory cell array including a plurality of memory blocks, each memory block including a plurality of memory cells, a plurality of word lines coupled to rows of the plurality of memory cells, a plurality of bit lines coupled to columns of the plurality of memory cells, and a control unit controlling an erase operation so that erase data is simultaneously written in the plurality of memory cells corresponding to an erase unit. A first erase mode may include a first erase unit and a first erase data pattern. A second erase mode may include a second erase unit and a second erase pattern. At least one of the first and second erase units and the first and second erase data patterns are different.
摘要翻译：存储器件包括存储单元阵列，该存储单元阵列包括多个存储器块，每个存储器块包括多个存储器单元，耦合到多个存储器单元中的行的多个字线，耦合到多个存储器单元的列的多个位线多个存储单元，以及控制擦除操作的控制单元，使得擦除数据被同时写入与擦除单元对应的多个存储单元中。第一擦除模式可以包括第一擦除单元和第一擦除数据模式。第二擦除模式可以包括第二擦除单元和第二擦除模式。第一和第二擦除单元以及第一和第二擦除数据模式中的至少一个是不同的。

2. 发明申请

US20130308370A1 MEMORY DEVICE AND SYSTEM WITH IMPROVED ERASE OPERATION 有权
标题翻译：具有改进的擦除操作的存储器件和系统
公开(公告)号：US20130308370A1
公开(公告)日：2013-11-21
申请号：US13948138
申请日：2013-07-22
申请人： Kwang-Jin Lee , Chang-Soo Lee , Joon-Min Park , Hui-Kwon Seo , Qi Wang
发明人： Kwang-Jin Lee , Chang-Soo Lee , Joon-Min Park , Hui-Kwon Seo , Qi Wang
IPC分类号： G11C13/00
CPC分类号： G11C13/0097 , G11C13/0004 , G11C13/0069 , G11C2013/0088 , G11C2211/5646
摘要： A memory device includes a memory cell array including a plurality of memory blocks, each memory block including a plurality of memory cells, a plurality of word lines coupled to rows of the plurality of memory cells, a plurality of bit lines coupled to columns of the plurality of memory cells, and a control unit controlling an erase operation so that erase data is simultaneously written in the plurality of memory cells corresponding to an erase unit. A first erase mode may include a first erase unit and a first erase data pattern. A second erase mode may include a second erase unit and a second erase pattern. At least one of the first and second erase units and the first and second erase data patterns are different.
摘要翻译：存储器件包括存储单元阵列，该存储单元阵列包括多个存储器块，每个存储器块包括多个存储器单元，耦合到多个存储器单元中的行的多个字线，耦合到多个存储器单元的列的多个位线多个存储单元，以及控制擦除操作的控制单元，使得擦除数据被同时写入与擦除单元对应的多个存储单元中。第一擦除模式可以包括第一擦除单元和第一擦除数据模式。第二擦除模式可以包括第二擦除单元和第二擦除模式。第一和第二擦除单元以及第一和第二擦除数据模式中的至少一个是不同的。

3. 发明授权

US08520446B2 Method of erasing a memory including first and second erase modes 有权
标题翻译：擦除包括第一和第二擦除模式的存储器的方法
公开(公告)号：US08520446B2
公开(公告)日：2013-08-27
申请号：US13535922
申请日：2012-06-28
申请人： Kwang-Jin Lee , Chang-Soo Lee , Joon-Min Park , Hui-Kwon Seo , Qi Wang
发明人： Kwang-Jin Lee , Chang-Soo Lee , Joon-Min Park , Hui-Kwon Seo , Qi Wang
IPC分类号： G11C16/04
CPC分类号： G11C13/0097 , G11C13/0004 , G11C13/0069 , G11C2013/0088 , G11C2211/5646
摘要： A memory device includes a memory cell array including a plurality of memory blocks, each memory block including a plurality of memory cells, a plurality of word lines coupled to rows of the plurality of memory cells, a plurality of bit lines coupled to columns of the plurality of memory cells, and a control unit controlling an erase operation so that erase data is simultaneously written in the plurality of memory cells corresponding to an erase unit. A first erase mode may include a first erase unit and a first erase data pattern. A second erase mode may include a second erase unit and a second erase pattern. At least one of the first and second erase units and the first and second erase data patterns are different.
摘要翻译：存储器件包括存储单元阵列，该存储单元阵列包括多个存储器块，每个存储器块包括多个存储器单元，耦合到多个存储器单元中的行的多个字线，耦合到多个存储器单元的列的多个位线多个存储单元，以及控制擦除操作的控制单元，使得擦除数据被同时写入与擦除单元对应的多个存储单元中。第一擦除模式可以包括第一擦除单元和第一擦除数据模式。第二擦除模式可以包括第二擦除单元和第二擦除模式。第一和第二擦除单元以及第一和第二擦除数据模式中的至少一个是不同的。

4. 发明申请

US20120269021A1 MEMORY DEVICE USING A VARIABLE RESISTIVE ELEMENT 有权
标题翻译：使用可变电阻元件的存储器件
公开(公告)号：US20120269021A1
公开(公告)日：2012-10-25
申请号：US13535922
申请日：2012-06-28
申请人： Kwang-Jin Lee , Chang-Soo Lee , Joon-Min Park , Hui-Kwon Seo , Qi Wang
发明人： Kwang-Jin Lee , Chang-Soo Lee , Joon-Min Park , Hui-Kwon Seo , Qi Wang
IPC分类号： G11C7/00
CPC分类号： G11C13/0097 , G11C13/0004 , G11C13/0069 , G11C2013/0088 , G11C2211/5646
摘要： A memory device includes a memory cell array including a plurality of memory blocks, each memory block including a plurality of memory cells, a plurality of word lines coupled to rows of the plurality of memory cells, a plurality of bit lines coupled to columns of the plurality of memory cells, and a control unit controlling an erase operation so that erase data is simultaneously written in the plurality of memory cells corresponding to an erase unit. A first erase mode may include a first erase unit and a first erase data pattern. A second erase mode may include a second erase unit and a second erase pattern. At least one of the first and second erase units and the first and second erase data patterns are different.
摘要翻译：存储器件包括存储单元阵列，该存储单元阵列包括多个存储器块，每个存储器块包括多个存储器单元，耦合到多个存储器单元中的行的多个字线，耦合到多个存储器单元的列的多个位线多个存储单元，以及控制擦除操作的控制单元，使得擦除数据被同时写入与擦除单元对应的多个存储单元中。第一擦除模式可以包括第一擦除单元和第一擦除数据模式。第二擦除模式可以包括第二擦除单元和第二擦除模式。第一和第二擦除单元以及第一和第二擦除数据模式中的至少一个是不同的。

5. 发明申请

US20100246239A1 Memory device using a variable resistive element 有权
标题翻译：使用可变电阻元件的存储器件
公开(公告)号：US20100246239A1
公开(公告)日：2010-09-30
申请号：US12659840
申请日：2010-03-23
申请人： Kwang-Jin Lee , Chang-Soo Lee , Joon-Min Park , Hui-Kwon Seo , Qi Wang
发明人： Kwang-Jin Lee , Chang-Soo Lee , Joon-Min Park , Hui-Kwon Seo , Qi Wang
IPC分类号： G11C11/00 , G11C7/00 , G11C8/00
CPC分类号： G11C13/0097 , G11C13/0004 , G11C13/0069 , G11C2013/0088 , G11C2211/5646
摘要： A memory device includes a memory cell array including a plurality of memory blocks, each memory block including a plurality of memory cells, a plurality of word lines coupled to rows of the plurality of memory cells, a plurality of bit lines coupled to columns of the plurality of memory cells, and a control unit controlling an erase operation so that erase data is simultaneously written in the plurality of memory cells corresponding to an erase unit. A first erase mode may include a first erase unit and a first erase data pattern. A second erase mode may include a second erase unit and a second erase pattern. At least one of the first and second erase units and the first and second erase data patterns are different.
摘要翻译：存储器件包括存储单元阵列，该存储单元阵列包括多个存储器块，每个存储器块包括多个存储器单元，耦合到多个存储器单元中的行的多个字线，耦合到多个存储器单元的列的多个位线多个存储单元，以及控制擦除操作的控制单元，使得擦除数据被同时写入与擦除单元对应的多个存储单元中。第一擦除模式可以包括第一擦除单元和第一擦除数据模式。第二擦除模式可以包括第二擦除单元和第二擦除模式。第一和第二擦除单元以及第一和第二擦除数据模式中的至少一个是不同的。

6. 发明授权

US08174878B2 Nonvolatile memory, memory system, and method of driving 有权
标题翻译：非易失性存储器，存储器系统和驾驶方法
公开(公告)号：US08174878B2
公开(公告)日：2012-05-08
申请号：US13053471
申请日：2011-03-22
申请人： Joon-Min Park , Kwang-Jin Lee , Du-Eung Kim , Woo-Yeong Cho , Hui-Kwon Seo
发明人： Joon-Min Park , Kwang-Jin Lee , Du-Eung Kim , Woo-Yeong Cho , Hui-Kwon Seo
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C13/0004 , G11C2213/72
摘要： Provided are a nonvolatile memory and related method of programming same. The nonvolatile memory includes a memory cell array with a plurality of nonvolatile memory cells and a write circuit. The write circuit is configured to write first logic state data to a first group of memory cells during a first program operation using an internally generated step-up voltage, and second logic state data to a second group of memory cells during a second program operation using an externally supplied step-up voltage.
摘要翻译：提供了一种非易失性存储器及其相关编程方法。非易失性存储器包括具有多个非易失性存储单元和写入电路的存储单元阵列。写电路被配置为在第一程序操作期间使用内部产生的升压电压将第一逻辑状态数据写入第一组存储器单元，并且在第二程序操作期间将第二逻辑状态数据写入第二组存储器单元外部提供的升压电压。

7. 发明授权

US07936619B2 Nonvolatile memory, memory system, and method of driving 失效
标题翻译：非易失性存储器，存储器系统和驾驶方法
公开(公告)号：US07936619B2
公开(公告)日：2011-05-03
申请号：US12339204
申请日：2008-12-19
申请人： Joon-Min Park , Kwang-Jin Lee , Du-Eung Kim , Woo-Yeong Cho , Hui-Kwon Seo
发明人： Joon-Min Park , Kwang-Jin Lee , Du-Eung Kim , Woo-Yeong Cho , Hui-Kwon Seo
IPC分类号： G11C7/00
CPC分类号： G11C13/0069 , G11C13/0004 , G11C2213/72
摘要： Provided are a nonvolatile memory and related method of programming same. The nonvolatile memory includes a memory cell array with a plurality of nonvolatile memory cells and a write circuit. The write circuit is configured to write first logic state data to a first group of memory cells during a first program operation using a first internally generated step-up voltage, and second logic state data to a second group of memory cells during a second program operation using an externally supplied step-up voltage.
摘要翻译：提供了一种非易失性存储器及其相关编程方法。非易失性存储器包括具有多个非易失性存储单元和写入电路的存储单元阵列。写入电路被配置为在第一编程操作期间使用第一内部产生的升压电压将第一逻辑状态数据写入第一组存储器单元，并且在第二编程操作期间将第二逻辑状态数据写入第二组存储器单元使用外部提供的升压电压。

8. 发明申请

US20100131708A1 Semiconductor device having resistance based memory array, method of reading and writing, and systems associated therewith 审中-公开
标题翻译：具有基于电阻的存储器阵列，读取和写入方法以及与其相关联的系统的半导体器件
公开(公告)号：US20100131708A1
公开(公告)日：2010-05-27
申请号：US12292896
申请日：2008-11-28
申请人： Joon-Min Park , Kwang Jin Lee , Beak-Hyung Cho
发明人： Joon-Min Park , Kwang Jin Lee , Beak-Hyung Cho
IPC分类号： G06F12/00
CPC分类号： G11C13/0069 , G11C15/046 , G11C2013/0076
摘要： In one embodiment, the semiconductor device includes a non-volatile memory cell array, a write buffer configured to store data being written into the non-volatile memory cell array, and a write address buffer configured to store a write address associated with each data stored in the write buffer. An output circuit is configured to selectively output one of data read from the non-volatile memory array and data from the write buffer. A by-pass control circuit is configured to control the output circuit based on whether an input read address matches a valid write address stored in the write address buffer. An invalidation unit is configured to invalidate an address stored in the write address buffer if the stored write address matches an input write address.
摘要翻译：在一个实施例中，半导体器件包括非易失性存储器单元阵列，被配置为存储被写入非易失性存储单元阵列的数据的写入缓冲器，以及写入地址缓冲器，被配置为存储与存储的每个数据相关联的写入地址在写缓冲区。输出电路被配置为选择性地输出从非易失性存储器阵列读取的数据和来自写入缓冲器的数据之一。旁路控制电路被配置为基于输入读取地址是否匹配存储在写入地址缓冲器中的有效写入地址来控制输出电路。如果所存储的写入地址与输入写入地址相匹配，则无效单元被配置为使存储在写入地址缓冲器中的地址无效。

9. 发明授权

US07843715B2 Memory cell of a resistive semiconductor memory device, a resistive semiconductor memory device having a three-dimensional stack structure, and related methods 有权
标题翻译：电阻半导体存储器件的存储单元，具有三维堆叠结构的电阻半导体存储器件及相关方法
公开(公告)号：US07843715B2
公开(公告)日：2010-11-30
申请号：US12015624
申请日：2008-01-17
申请人： Joon-Min Park , Sang-Beom Kang , Hyung-Rok Oh , Woo-Yeong Cho
发明人： Joon-Min Park , Sang-Beom Kang , Hyung-Rok Oh , Woo-Yeong Cho
IPC分类号： G11C5/02
CPC分类号： G11C5/02 , G11C13/00 , G11C13/0004 , G11C13/0023 , G11C2213/71 , G11C2213/72
摘要： A memory cell of a resistive semiconductor memory device, a resistive semiconductor memory device having a three-dimensional stack structure, and related methods are provided. The memory cell of a resistive semiconductor memory device includes a twin cell, wherein the twin cell stores data values representing one bit of data. The twin cell includes a main unit cell connected to a main bit line and a word line, and a sub unit cell connected to a sub bit line and the word line. Also, the main unit cell includes a first variable resistor and a first diode, and the sub unit cell includes a second variable resistor and a second diode.
摘要翻译：提供了电阻半导体存储器件的存储单元，具有三维堆叠结构的电阻半导体存储器件及相关方法。电阻半导体存储器件的存储单元包括双胞胎，其中双胞胎存储表示一位数据的数据值。双胞胎单元包括连接到主位线和字线的主单元，以及连接到子位线和字线的子单元。此外，主单元包括第一可变电阻器和第一二极管，并且子单元电池包括第二可变电阻器和第二二极管。

10. 发明授权

US07808811B2 Resistance semiconductor memory device having three-dimensional stack and word line decoding method thereof 有权
标题翻译：具有三维堆叠和字线解码方法的电阻半导体存储器件
公开(公告)号：US07808811B2
公开(公告)日：2010-10-05
申请号：US12020237
申请日：2008-01-25
申请人： Joon-Min Park , Sang-Beom Kang , Hyung-Rok Oh , Woo-Yeong Cho
发明人： Joon-Min Park , Sang-Beom Kang , Hyung-Rok Oh , Woo-Yeong Cho
IPC分类号： G11C11/00
CPC分类号： G11C8/08 , G11C8/14 , G11C11/16 , G11C13/00 , G11C13/0004 , G11C13/0023 , G11C13/0028 , G11C2213/71 , G11C2213/72
摘要： A resistance semiconductor memory device of a three-dimensional stack structure, and a word line decoding method thereof, are provided. In the resistance semiconductor memory device of a three-dimensional stack structure, in which a plurality of word line layers and a plurality of bit line layers are disposed alternately and perpendicularly, and in which a plurality of memory cell layers are disposed between the word line layers and the bit line layers; the resistance semiconductor memory device includes a plurality of bit lines disposed on each of the bit line layers in a first direction as a length direction; a plurality of sub word lines disposed on each of the word line layers in a second direction as a length direction, intersected to the first direction; a plurality of memory cells disposed on the memory cell layers; and a plurality of main word lines individually disposed on a main word line layer specifically adapted over the bit line layers and the word line layers, in the second direction as a length direction, each one of the plurality of main word lines being shared by a predetermined number of sub word lines. An efficient word line decoding adequate to high integration can be achieved.
摘要翻译：提供三维堆栈结构的电阻半导体存储器件及其字线解码方法。在三维堆叠结构的电阻半导体存储器件中，其中多个字线层和多个位线层交替和垂直地布置，并且其中多个存储单元层设置在字线层和位线层; 电阻半导体存储器件包括沿着第一方向设置在每个位线层上的多个位线作为长度方向; 在与第一方向相交的长度方向的第二方向上配置在每个字线层上的多个子字线; 设置在所述存储单元层上的多个存储单元; 以及多个主字线分别设置在主字线层上，特别适用于位线层和字线层，在第二方向上作为长度方向，多个主字线中的每一条由预定数量的子字线。可以实现足够高集成度的有效的字线解码。

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