专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20080055415A1 IMAGE RECORDING AND REPRODUCING APPARATUS 失效
标题翻译：图像记录和再现设备
公开(公告)号：US20080055415A1
公开(公告)日：2008-03-06
申请号：US11850858
申请日：2007-09-06
申请人： Michihiro FUJIYAMA , Daisuke NAKAJIMA
发明人： Michihiro FUJIYAMA , Daisuke NAKAJIMA
IPC分类号： H04N5/225
CPC分类号： H04N5/76 , G08B13/19673 , G11B27/002 , G11B2220/41 , H04N5/781 , H04N5/783 , H04N9/8205 , H04N9/8227
摘要： An image recording and reproducing apparatus includes a group management information file creation circuit for, in recording, grouping recorded images at predetermined time intervals and creating, for each group, a group management information file storing group management information including a start time indicating the time when a first recorded image in a group is recorded, an end time indicating the time when a last recorded image in the group is recorded, an address at which index information about the first recorded image in the group is stored, and channel distance information indicating, for each channel, a group interval from a group including a last recorded image of a channel to the current group.
摘要翻译：图像记录和再现装置包括：组管理信息文件创建电路，用于以预定的时间间隔对记录的图像进行记录分组，并且为每个组创建存储组管理信息的组管理信息文件，组管理信息文件包括指示时间记录组中的第一记录图像，指示记录组中最后记录图像的时间的结束时间，存储关于组中的第一记录图像的索引信息的地址，以及指示，对于每个通道，从包括通道的最后记录图像的组的组间隔到当前组。

2. 发明申请

US20080225886A1 SERIAL COMMUNICATION SYSTEM 失效
标题翻译：串行通信系统
公开(公告)号：US20080225886A1
公开(公告)日：2008-09-18
申请号：US12048809
申请日：2008-03-14
申请人： Michihiro FUJIYAMA
发明人： Michihiro FUJIYAMA
IPC分类号： H04J15/00
CPC分类号： G06F13/4291
摘要： A serial communication system includes a master processor and a slave processor. A CS signal for requesting a serial communication is output from the master processor, and an OK_INV signal for responding to the CS signal is output from the slave processor. When a CS signal is an active state, the master processor executes a serial communications of a preset number of bits every time that a level of the OK_INV signal is reversed. The slave processor inverts a level of an OK_INV signal in response to the CS signal shifting to the active state. The slave processor changes the level of the OK_INV signal every time that a serial communication of a preset number of bits is completed.
摘要翻译：串行通信系统包括主处理器和从属处理器。从主处理器输出用于请求串行通信的CS信号，并且从从属处理器输出用于响应CS信号的OK_INV信号。当CS信号是活动状态时，主处理器每当OK_INV信号的电平反转时执行预置位数的串行通信。响应于CS信号转换到活动状态，从属处理器反转OK_INV信号的电平。每当完成预置位数的串行通信时，从器件处理器改变OK_INV信号的电平。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式