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1. 发明专利

AU637262B2 RATE CONVERSION APPARATUS 未知
公开(公告)号：AU637262B2
公开(公告)日：1993-05-20
申请号：AU8561691
申请日：1991-10-04
申请人： NEC CORPORATION
发明人： OSAMU ICHIYOSHI
IPC分类号： H03L7/08 , H03L7/099 , H03L7/16 , H04L7/00 , H04L25/05
摘要： A first clock signal of f1 in frequency is converted into a second clock signal having a frequency of f2 = n/m f1. The first clock signal is converted by a tank circuit (12) and a converter (13) into an R-bit first phase signal ( theta 1) indicating the phase of the first clock signal. The first phase signal is multiplied by n (mod 2 ) by a multiplier into a second phase signal ( theta 3). The second phase signal is supplied to a digital phase-locked loop (PIL) (3) consisting of a subtractor (15), a low-pass filter (LPF) (16), a numerically controlled oscillator (NCO) (17) and a multiplier (18). The multiplier in the digital PIL (3) multiplies by m (mod 2 ) a third phase signal, indicating the phase of a second clock signal which is the output of the NCO (17), to generate a fourth phase signal. The subtractor (15) generates a signal representing the phase error between the second and fourth phase signals. This phase error signal is filtered by the LPF (16) to control the oscillating phase of the NCO (17). A clock generating circuit generates, on the basic of the third phase, signal, the second clock signal.

2. 发明专利

AU2609892A PHASE-LOCKED CIRCUIT CAPABLE OF BEING QUICKLY PUT IN A PHASE-LOCKED STATE 未知
公开(公告)号：AU2609892A
公开(公告)日：1993-04-01
申请号：AU2609892
申请日：1992-09-30
申请人： NEC CORPORATION
发明人： OSAMU ICHIYOSHI
IPC分类号： H03L7/087 , H03L7/099

3. 发明专利

AU639874B2 A DEMODULATION CIRCUIT 未知
公开(公告)号：AU639874B2
公开(公告)日：1993-08-05
申请号：AU8678091
申请日：1991-10-25
申请人： NEC CORPORATION
发明人： OSAMU ICHIYOSHI
IPC分类号： H04L27/227 , H03L7/099 , H04L7/00 , H04L7/02 , H04L7/027 , H04L7/033 , H04L27/00 , H04L27/22 , H04L27/233
摘要： A digital output of a quasi-coherent detection circuit (2) is M-th power multiplied and then processed by a set of digital filters to generate signals for coherent detection and clock interpolation. The digital output of the quasi-coherent detection circuit (2) is also fed, through a delay circuit (19), to coherent detection circuit which in turn processes the digital output of the quasi-coherent detection circuit, using the coherent detection signal. Timing error information indicative of the difference between phases of an interpolated clock and the interpolation signal determines the weighting factor of data interpolation channel filter (18) which in turn interpolate and output coherent-detected data signal.

4. 发明专利

AU2531592A METHOD AND ARRANGEMENT OF COHERENTLY DEMODULATING PSK SIGNALS USING A FEEDBACK LOOP INCLUDING A FILTER BANK 未知
公开(公告)号：AU2531592A
公开(公告)日：1993-06-10
申请号：AU2531592
申请日：1992-09-22
申请人： NEC CORPORATION
发明人： OSAMU ICHIYOSHI
IPC分类号： H04L27/227 , H04L27/00 , H04L27/22 , H04L27/233

5. 发明专利

AU632940B2 PHASE-LOCK LOOP DEVICE OPERABLE AT A HIGH SPEED 未知
公开(公告)号：AU632940B2
公开(公告)日：1993-01-14
申请号：AU7730491
申请日：1991-05-23
申请人： NEC CORPORATION
发明人： OSAMU ICHIYOSHI
IPC分类号： H03D13/00 , H03H17/02 , H03L7/00
摘要： In a phase-lock loop device for phase locking a device input signal (11) representing a first complex number and having a device input phase which should be locked into a locked phase, a first complex multiplier (14) calculates a first product of the first complex number and a first conjugate complex number to produce a first complex product signal. The first conjugate complex number is represented by a first conjugate signal which is produced by delaying and processing the device input signal. A second complex multiplier (18) calculates a second product of a phase processed signal and a multiplier input signal to produce a second complex product signal. The phase processed signal is produced by filtering and processing the first complex product signal. The multiplier input signal is produced by delaying and limiting the second complex product signal. A third complex multiplier (22) calculates a third product of the first complex number and a second conjugate complex number to produce a third complex product signal. The second conjugate complex number is represented by a second conjugate signal which is produced by processing the second complex product signal. A fourth complex multiplier (24) calculates a fourth product of the second complex product signal and a filtered signal to produce a fourth complex product signal having the locked phase. The filtered signal is produced by filtering the third complex product signal.

6. 发明专利

AU2609792A PHASE DIVIDER FOR COMPLEX SIGNALS 未知
公开(公告)号：AU2609792A
公开(公告)日：1993-04-01
申请号：AU2609792
申请日：1992-09-30
申请人： NEC CORPORATION
发明人： OSAMU ICHIYOSHI
IPC分类号： H03H17/08 , H04L27/00 , H04L27/22 , H04L27/227 , H04L27/233
摘要： In a phase divider, a complex signal containing a sequence of samples of real and imaginary values is limited to a unit amplitude and multiplied by a first complex multiplier with a first feedback complex signal, the output the multiplier being fed through a loop filter to a second complex multiplier where the signal is multiplied with a second feedback complex signal. The output of the second multiplier is limited to a unit amplitude, delayed by a sample interval and applied to the second complex multiplier as the second feedback complex signal. The first feedback complex signal is derived by a circuit that raises the frequency the delayed signal by a desired factor.

7. 发明专利

AU2531392A DEMODULATOR FOR CONTINUOUSLY AND ACCURATELY CARRYING OUT DEMODULATING OPERATION BY A FREQUENCY MULTIPLICATION METHOD 未知
公开(公告)号：AU2531392A
公开(公告)日：1993-03-25
申请号：AU2531392
申请日：1992-09-22
申请人： NEC CORPORATION
发明人： OSAMU ICHIYOSHI
IPC分类号： H04L27/227 , H04L27/00 , H04L27/22 , H04L27/233

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