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1. 发明专利

JP2011163898A Semiconductor integrated circuit and method for testing the same 有权
标题翻译：半导体集成电路及其测试方法
公开(公告)号：JP2011163898A
公开(公告)日：2011-08-25
申请号：JP2010026444
申请日：2010-02-09
申请人： Nec Corp , 日本電気株式会社
发明人： INUI SHIGETO
IPC分类号： G01R31/30 , G01R31/28 , H01L21/66 , H01L21/822 , H01L27/04
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit for detecting a degradation phenomenon in an electromigration under the actual operation condition, an detecting a sign of a failure.
SOLUTION: The semiconductor integrated circuit 10 includes: a counter circuit 6; a delay element 5 for generating a delayed clock signal 56; a first flip-flop 1 for inputting a data toggled in each clock cycle of a clock signal 52; wiring 4 for inputting an output signal from the first flip-flop 1; a second flip-flop 2 driven based on the delayed clock signal 56, and inputting an output signal from the wiring 4; a third flip-flop 3 driven based on the clock signal 52, and inputting the output signal from the first flip-flop 1; and an exclusive-OR circuit 7 for outputting an exclusive-OR of output signals from the second and third flip-flops 2, 3.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供一种用于在实际操作条件下检测电迁移中的劣化现象的半导体集成电路，检测故障的迹象。解决方案：半导体集成电路10包括：计数器电路6; 用于产生延迟时钟信号56的延迟元件5; 用于输入在时钟信号52的每个时钟周期中切换的数据的第一触发器1; 布线4，用于输入来自第一触发器1的输出信号; 基于延迟时钟信号56驱动的第二触发器2，并且从布线4输入输出信号; 基于时钟信号52驱动的第三触发器3，并输入来自第一触发器1的输出信号; 以及用于输出来自第二和第三触发器2,3的输出信号的异或的异或电路7。版权所有：（C）2011，JPO＆INPIT

2. 发明专利

JP2009176832A Deterioration detection circuit and semiconductor integrated circuit 有权
标题翻译：检测检测电路和半导体集成电路
公开(公告)号：JP2009176832A
公开(公告)日：2009-08-06
申请号：JP2008011853
申请日：2008-01-22
申请人： Nec Corp , 日本電気株式会社
发明人： INUI SHIGETO
IPC分类号： H01L21/822 , G01R31/28 , H01L21/66 , H01L27/04
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit which can detect electromigration deterioration phenomenon in an LSI after shipping.
SOLUTION: The semiconductor integrated circuit includes N deterioration detection circuits (1) (N: integer of 2 or more) to detect the deterioration of wiring caused by electromigration. The deterioration detection circuit (1) includes a frequency doubling circuit (10) which inputs a clock signal and generates a double frequency signal with 2-fold frequency of the clock signal, a frequency dividing circuit (11) to generate a frequency dividing signal with a halved frequency of a clock signal, a test circuit (17) which inputs a frequency dividing signal and detects the deterioration of wiring, and a heater circuit (16) which inputs the double frequency signal and heats the test circuit (17).
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一种在运输之后可以检测LSI中的电迁移退化现象的半导体集成电路。解决方案：半导体集成电路包括N个劣化检测电路（1）（N：2以上的整数），以检测由电迁移引起的布线的劣化。劣化检测电路（1）包括输入时钟信号并产生时钟信号的2倍频率的双频信号的倍频电路（10），分频电路（11），生成具有时钟信号的一半的频率，输入分频信号并检测布线的劣化的测试电路（17），以及输入双频信号并加热测试电路（17）的加热器电路（16）。版权所有（C）2009，JPO＆INPIT

3. 发明专利

JP2017078928A 情報処理装置、情報処理方法、及び、プログラム有权
公开(公告)号：JP2017078928A
公开(公告)日：2017-04-27
申请号：JP2015206096
申请日：2015-10-20
申请人：日本電気株式会社 , Nec Corp
发明人： INUI SHIGETO
IPC分类号： G06F7/38
摘要：【課題】区間の端部での値を保証し、偽のアンダーフローを発生させない値を算出する情報処理装置を提供する。【解決手段】情報処理装置は、入力データ100が入力データの区間の端部のデータであるか否かを検出する端部検出部14と、所定の第1の関数に対する近似値を算出する第2の関数に入力データを適用した算出結果である加算結果が、入力データを第1の関数に適用した場合に発生しないアンダーフローである偽のアンダーフローを発生させるか否かを検知し、加算結果が偽のアンダーフローを発生させる場合に、加算結果を偽のアンダーフローを発生させない値に修正するアンダーフロー検知部15と、入力データが端部のデータの場合、端部に対応した所定のデータを選択し、入力データが端部のデータでない場合、加算結果を選択する選択部16と、を含む。【選択図】図1

4. 发明专利

JP2012113510A Wiring verification method, wiring verification device and wiring verification program for semiconductor integrated circuit 有权
标题翻译：接线验证方法，接线验证设备和半导体集成电路的接线验证程序
公开(公告)号：JP2012113510A
公开(公告)日：2012-06-14
申请号：JP2010261898
申请日：2010-11-25
申请人： Nec Corp , 日本電気株式会社
发明人： INUI SHIGETO
IPC分类号： G06F17/50 , H01L21/82
CPC分类号： G06F17/5036 , G06F2217/82
摘要： PROBLEM TO BE SOLVED: To provide a wiring verification method for quickly verifying the electro-migration tolerance of wiring without increasing any constraint on design.SOLUTION: In this wiring verification method, Iavg/Irms values of wiring are calculated by using a netlist and wiring capacity/resistance information of a verification object circuit, and when the calculated Iavg/Irms values of wiring exceed predetermined Iavg/Irms normal values, the Irms normal value is relaxed, and the Iavg normal value is restricted in accordance with the relaxed Irms normal value, and whether or not a wiring lifetime calculated by using the predetermined Irms normal value and the relaxed Irms normal value fulfills a predetermined normal value of the wiring lifetime is verified, and whether or not each of the calculated Iavg/Irms values of wiring exceeds the restricted Iavg normal value and the relaxed Irms normal value is verified again.
摘要翻译：要解决的问题：提供一种用于快速验证布线的电迁移公差的布线验证方法，而不增加对设计的任何限制。解决方案：在该接线验证方法中，通过使用验证对象电路的网表和布线容量/电阻信息计算布线的Iavg / Irms值，并且当布线的计算的Iavg / Irms值超过预定的Iavg / Irms 正常值，Irms正常值被放宽，并且根据放宽的Irms正常值来限制Iavg正常值，并且通过使用预定的Irms正常值和放宽的Irms正常值计算的布线寿命是否满足预定的验证布线寿命的正常值，并且每次计算的布线的Iavg / Irms值是否超过限制的Iavg正常值，并且再次验证放宽的Irms正常值。版权所有（C）2012，JPO＆INPIT

5. 发明专利

JP2010124403A Semiconductor integrated circuit and designing method of the same 审中-公开
标题翻译：半导体集成电路及其设计方法
公开(公告)号：JP2010124403A
公开(公告)日：2010-06-03
申请号：JP2008298291
申请日：2008-11-21
申请人： Nec Corp , 日本電気株式会社
发明人： INUI SHIGETO
IPC分类号： H03K3/037
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit, and to provide a designing method for the circuit having high performance.
SOLUTION: A semiconductor integrated circuit includes: a logic circuit (first circuit 1) for generating an enable signal, indicating whether a clock is valid/invalid from an input signal; a clock gating circuit (AND circuit 20) for inputting the enable signal and a clock signal and outputting a gated clock signal; a buffer circuit 21 for inputting a clock signal and outputting a buffered clock signal; a first low-through latch group (low-through latch 10) for inputting the gated clock signal; a high-through latch group (high-through latch 12) for inputting the gated clock signal; and a second low-through latch group (low-through latch 11) for inputting the buffered clock signal.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种半导体集成电路，并提供具有高性能的电路的设计方法。解决方案：半导体集成电路包括：逻辑电路（第一电路1），用于产生使能信号，指示时钟是否从输入信号有效/无效; 时钟选通电路（AND电路20），用于输入使能信号和时钟信号并输出门控时钟信号; 缓冲电路21，用于输入时钟信号并输出缓冲的时钟信号; 用于输入门控时钟信号的第一低通闩锁组（低通锁存器10）用于输入门控时钟信号的高通过锁存器组（高通过锁存器12）以及用于输入缓冲的时钟信号的第二低通闩锁组（低通锁存器11）。版权所有（C）2010，JPO＆INPIT

6. 发明专利

JP2005277909A Logical circuit, and system, method, and program for designing logical circuit 有权
标题翻译：逻辑电路，以及用于设计逻辑电路的系统，方法和程序
公开(公告)号：JP2005277909A
公开(公告)日：2005-10-06
申请号：JP2004089750
申请日：2004-03-25
申请人： Nec Corp , 日本電気株式会社
发明人： INUI SHIGETO , HAGIWARA YASUHIKO
IPC分类号： G06F17/50 , H01L21/82 , H01L21/822 , H01L27/04 , H03K3/012 , H03K3/037 , H03K3/12 , H03K17/693 , H03K19/00
CPC分类号： G06F17/505 , H03K3/012 , H03K3/037 , H03K17/693
摘要： PROBLEM TO BE SOLVED: To provide a latch circuit constituting a high-speed pipeline.
SOLUTION: The latching circuit is prepared by which a latch circuit with a high-speed through-delay is obtained by being added to a basic logical circuit. Then a means is provided which obtains a latch circuit position to maximally absorb the deviation of a clock edge such as skew or jitter, and constitutes the latch circuit by adding the latching circuit to the basic logical circuit which is positioned at an obtained point. Accordingly, the latch circuit is designed which is not maximally affected by the skew or the jitter.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供构成高速管道的锁存电路。解决方案：通过添加到基本逻辑电路来获得具有高速通过延迟的锁存电路的锁存电路。然后提供一种获得锁存电路位置以最大限度地吸收诸如歪斜或抖动之类的时钟沿的偏差的装置，并通过将锁存电路加到位于获得点处的基本逻辑电路来构成锁存电路。因此，锁存电路被设计成不受歪斜或抖动影响最大。版权所有（C）2006，JPO＆NCIPI

7. 发明专利

JP2000163251A ADDER 失效
公开(公告)号：JP2000163251A
公开(公告)日：2000-06-16
申请号：JP35533398
申请日：1998-11-30
申请人： NEC CORP
发明人： INUI SHIGETO
IPC分类号： G06F7/50 , G06F7/508 , H03K19/096
摘要： PROBLEM TO BE SOLVED: To accelerate the operation speed of a carry lookahead type adder. SOLUTION: A pg generation circuit 301 makes two binaries of n digits (4

8. 发明专利

JPH09222993A DIVIDER 失效
公开(公告)号：JPH09222993A
公开(公告)日：1997-08-26
申请号：JP4964896
申请日：1996-02-14
申请人： NEC CORP
发明人： INUI SHIGETO
IPC分类号： G06F7/496 , G06F7/506 , G06F7/52 , G06F7/535
摘要： PROBLEM TO BE SOLVED: To accelerate speed by reducing processing for making a partial remainder into two complements required before the decision of quotient concerning division to use redundant binary expressions for a high-radix subtraction shift system and the partial remainder. SOLUTION: A high-order partial remainder register 2 holds the high-order bits of the partial remainder in the expression of two complements, and a low- order partial remainder register 3 holds the low-order bits of the partial remainder in the redundant binary expression. Then, the output of the high-order partial remainder register is directly connected to a quotient generation circuit 5. Among the outputs of a two-bit shifter 9, the most significant two bits of digit overflow and the output of a two-bit shifter 8 are connected to a two- complement converting circuit 6, the output of the two-complement converting circuit 6 and the high-order bits of output from a multiple selector 21 for a divider are connected to a high-order partial remainder generation two- complement subtracter 18, and the output of the two-bit shifter 9 and the low- order bits of output of the multiple selector 21 are connected to a low-order partial remainder generation redundant binary subtracter 19.

9. 发明专利

JPH0793135A SUBTRACTION SHIFT TYPE DIVIDER 失效
公开(公告)号：JPH0793135A
公开(公告)日：1995-04-07
申请号：JP23613093
申请日：1993-09-22
申请人： NEC CORP
发明人： INUI SHIGETO
IPC分类号： G06F7/49 , G06F7/52 , G06F7/535
摘要： PURPOSE:To reduce the delay time of quotient generation by parallelly executing division at a low base within the time for the multiple generation of a divisor before the start of division in the case of division with high base subtraction shift type divider technique. CONSTITUTION:The multiple of '3' is generated by a '3' multiple generation block 14 for the divisor parallelly with the division of a base 2 due to a division block 11 for the base 2, and a multiple 103 of '3', partial remainder R(1) and quotient q(1) required for the division of a base 4 are generated. Next, the multiples of '5' and '7' are generated by a 5 and 7 multiple generation block 15 for the divisor parallelly with the division of the base 4 due to a division block 12 for the base 4, and a multiple 105 of '5', multiple 106 of '7' of the divisor, partial remainder R(2) and quotients q(2) and q(3) are calculated. Afterwards, a base 8 is repeatedly divided by a division block 13 for the base 8 while using the multiples of '3', '5' and '7' of the divisor. Before the division at the base 8 is started, the multiple required for the division is generated parallelly with the generation of high-order 3 bits in the quotient.

10. 发明专利

JP2001222410A DIVIDER 失效
公开(公告)号：JP2001222410A
公开(公告)日：2001-08-17
申请号：JP2000029524
申请日：2000-02-07
申请人： NEC CORP
发明人： INUI SHIGETO
IPC分类号： G06F7/537 , G06F7/483 , G06F7/52 , G06F7/535
摘要： PROBLEM TO BE SOLVED: To quickly generate a quotient in a divider of a high radix subtraction shift type performing scaling to a divisor and using redundant binary expression to a partial remainder. SOLUTION: This high radix type divider for deciding a quotient by referring to a divisor and dividend normalized so as to be ranging from not less than 1/2k to less than 1/2k+1 with k as a positive integer and bit length to be decided according to the radix of an arithmetic operation and the maximum digit number among all the bits of a partial remainder is provided with a scaling factor generating part for generating a multiplication coefficient for scaling the divisor within a prescribed range, a multiplying part for multiplying each divisor and dividend by the multiplication coefficient, a divisor 3 magnification generating part for generating the 3 magnification of the divisor multiplied by the multiplication coefficient, and a repeated arithmetic part for generating the upper bits of the partial remainder with 4 bits turned into two complements by referring to the number of the upper bits with arbitrary length of the partial remainder and generating the quotient by referring to the upper 4 bits of the partial remainder.

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