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1. 发明授权

US08832412B2 Scalable processing unit 有权
标题翻译：可扩展处理单元
公开(公告)号：US08832412B2
公开(公告)日：2014-09-09
申请号：US13236822
申请日：2011-09-20
申请人： Neil Bailey , Eben Upton
发明人： Neil Bailey , Eben Upton
IPC分类号： G06F15/16 , G06F13/14 , H04N7/26 , G06F13/364
CPC分类号： H04N19/182 , G06F13/364 , G06F15/16 , H04N19/127 , H04N19/156 , H04N19/187 , H04N19/439 , Y02D10/14
摘要： Various methods and systems are provided for processing units that may be scaled. In one embodiment, a processing unit includes a plurality of scalar processing units and a vector processing unit in communication with each of the plurality of scalar processing units. The vector processing unit is configured to coordinate execution of instructions received from the plurality of scalar processing units. In another embodiment, a scalar instruction packet including a pre-fix instruction and a vector instruction packet including a vector instruction is obtained. Execution of the vector instruction may be modified by the pre-fix instruction in a processing unit including a vector processing unit. In another embodiment, a scalar instruction packet including a plurality of partitions is obtained. The location of the partitions is determined based upon a partition indicator included in the scalar instruction packet and a scalar instruction included in a partition is executed by a processing unit.
摘要翻译：为可缩放的处理单元提供了各种方法和系统。在一个实施例中，处理单元包括与多个标量处理单元中的每一个通信的多个标量处理单元和向量处理单元。矢量处理单元被配置为协调从多个标量处理单元接收的指令的执行。在另一个实施例中，获得包括预固定指令和包括向量指令的向量指令分组的标量指令分组。矢量指令的执行可以通过包括矢量处理单元的处理单元中的预定指令进行修改。在另一个实施例中，获得包括多个分区的标量指令分组。基于包括在标量指令包中的分区指示符来确定分区的位置，并且由处理单元执行包括在分区中的标量指令。

2. 发明授权

US08285975B2 Register file with separate registers for compiler code and low level code 有权
标题翻译：使用单独的寄存器为编译器代码和低级代码注册文件
公开(公告)号：US08285975B2
公开(公告)日：2012-10-09
申请号：US10413488
申请日：2003-04-15
申请人： Stephen Barlow , Neil Bailey , Timothy Ramsdale , David Plowman , Robert Swann
发明人： Stephen Barlow , Neil Bailey , Timothy Ramsdale , David Plowman , Robert Swann
IPC分类号： G06F9/30
CPC分类号： G06F9/30138 , G06F9/30036 , G06F9/30101 , G06F9/30149
摘要： A processor core comprising an execution unit and a register file, said register file comprising a first plurality of registers accessible to a compiler generated code and a second plurality of registers which can not be accessed by a compiler generated code, whereby the registers of said second plurality of registers are accessible to a low level code.
摘要翻译：一种处理器核心，包括执行单元和寄存器文件，所述寄存器文件包括编译器生成的代码可访问的第一多个寄存器和不能被编译器生成的代码访问的第二多个寄存器，由此所述第二个寄存器的寄存器多个寄存器可被低级代码访问。

3. 发明申请

US20120030465A1 Indirect Pairing of Communication Devices 有权
标题翻译：通讯设备间接配对
公开(公告)号：US20120030465A1
公开(公告)日：2012-02-02
申请号：US13004667
申请日：2011-01-11
申请人： Neil Bailey
发明人： Neil Bailey
IPC分类号： H04W12/06 , H04L9/00 , H04B7/00
CPC分类号： H04W76/10 , H04W12/06
摘要： A method for establishing a communication link between two devices, the communication link employing a protocol that provides for link establishment information sufficient for establishing a link between two devices to be negotiated between those devices; the method comprising: establishing communication links between each of the two devices and one or more further devices; transmitting from the one or more further devices to each of the two devices information that defines link establishment parameters for a link between the two devices; and establishing the link between the two devices using the defined link establishment parameters.
摘要翻译：一种用于在两个设备之间建立通信链路的方法，所述通信链路采用提供足以在这些设备之间协商的两个设备之间建立链路的链路建立信息的协议; 所述方法包括：在所述两个设备中的每一个与一个或多个其他设备之间建立通信链路; 从所述一个或多个其他设备向所述两个设备中的每一个发送定义所述两个设备之间的链路的链路建立参数的信息; 以及使用所定义的链路建立参数建立两个设备之间的链路。

4. 发明申请

US20110249744A1 Method and System for Video Processing Utilizing N Scalar Cores and a Single Vector Core 审中-公开
标题翻译：使用N个标准核心和单个矢量核心的视频处理方法和系统
公开(公告)号：US20110249744A1
公开(公告)日：2011-10-13
申请号：US12977483
申请日：2010-12-23
申请人： Neil Bailey
发明人： Neil Bailey
IPC分类号： H04N7/26
CPC分类号： H04N19/42 , G06F9/3891 , H04N21/426
摘要： A multimedia processor may comprise a first scalar core, a second scalar core, and a vector core integrated on a single substrate of said multimedia processor. The multimedia processor may receive data and instructions associated with image processing. The multimedia processor may configure the received data and instructions into data and instructions associated with a first image processing program and into data and instructions associated with a second image processing program independent of the first image processing program. The first image processing program may be configured to be handled by the first scalar core and the vector core, while the data and instructions associated with the second image processing program may be configured to be handled by the second scalar core and the vector core. The vector core may communicate data to and from register files in each of the first and second scalar cores.
摘要翻译：多媒体处理器可以包括集成在所述多媒体处理器的单个基板上的第一标量核心，第二标量核心和矢量核心。多媒体处理器可以接收与图像处理相关联的数据和指令。多媒体处理器可以将接收到的数据和指令配置成与第一图像处理程序相关联的数据和指令，以及与第一图像处理程序无关的与第二图像处理程序相关联的数据和指令。第一图像处理程序可以被配置为由第一标量核和向量核处理，而与第二图像处理程序相关联的数据和指令可以被配置为由第二标量核和向量核来处理。矢量核心可以向第一和第二标量核心中的每一个中的寄存器文件传送数据。

5. 发明申请

US20070061550A1 INSTRUCTION EXECUTION IN A PROCESSOR 有权
标题翻译：处理者的指示执行
公开(公告)号：US20070061550A1
公开(公告)日：2007-03-15
申请号：US11556937
申请日：2006-11-06
申请人： Stephen Barlow , Neil Bailey , Timothy Ramsdale , David Plowman , Robert Swann
发明人： Stephen Barlow , Neil Bailey , Timothy Ramsdale , David Plowman , Robert Swann
IPC分类号： G06F15/00
CPC分类号： G06F9/30036 , G06F9/30021 , G06F9/3013 , G06F9/30185 , G06F9/3889 , G06F15/8076
摘要： A processor comprising: a scalar processing unit for executing scalar instructions each defining a single value pair; a vector processing unit for executing vector instructions each defining multiple value pairs, the vector processing unit comprising a plurality of value processing units each operable to process one of said multiple value pairs and to generate a respective result; and an instruction decoder for receiving a single stream of instructions including scalar instructions and vector instructions and operable to direct scalar instructions to the scalar unit and vector instructions to the vector unit.
摘要翻译：一种处理器，包括：标量处理单元，用于执行每个定义单个值对的标量指令; 矢量处理单元，用于执行各自定义多个值对的矢量指令，所述矢量处理单元包括多个值处理单元，每个所述值处理单元可操作以处理所述多个值对之一并产生相应的结果; 以及指令解码器，用于接收包括标量指令和向量指令的单个指令流，并且可操作以将标量指令引导到标量单元，并向矢量单元指示矢量指令。

6. 发明申请

US20130024652A1 Scalable Processing Unit 有权
标题翻译：可扩展处理单元
公开(公告)号：US20130024652A1
公开(公告)日：2013-01-24
申请号：US13236822
申请日：2011-09-20
申请人： Neil Bailey , Eben Upton
发明人： Neil Bailey , Eben Upton
IPC分类号： G06F15/76 , G06F9/06
CPC分类号： H04N19/182 , G06F13/364 , G06F15/16 , H04N19/127 , H04N19/156 , H04N19/187 , H04N19/439 , Y02D10/14
摘要： Various methods and systems are provided for processing units that may be scaled. In one embodiment, a processing unit includes a plurality of scalar processing units and a vector processing unit in communication with each of the plurality of scalar processing units. The vector processing unit is configured to coordinate execution of instructions received from the plurality of scalar processing units. In another embodiment, a scalar instruction packet including a pre-fix instruction and a vector instruction packet including a vector instruction is obtained. Execution of the vector instruction may be modified by the pre-fix instruction in a processing unit including a vector processing unit. In another embodiment, a scalar instruction packet including a plurality of partitions is obtained. The location of the partitions is determined based upon a partition indicator included in the scalar instruction packet and a scalar instruction included in a partition is executed by a processing unit.
摘要翻译：为可缩放的处理单元提供了各种方法和系统。在一个实施例中，处理单元包括与多个标量处理单元中的每一个通信的多个标量处理单元和向量处理单元。矢量处理单元被配置为协调从多个标量处理单元接收的指令的执行。在另一个实施例中，获得包括预固定指令和包括向量指令的向量指令分组的标量指令分组。矢量指令的执行可以通过包括矢量处理单元的处理单元中的预定指令进行修改。在另一个实施例中，获得包括多个分区的标量指令分组。基于包括在标量指令包中的分区指示符来确定分区的位置，并且由处理单元执行包括在分区中的标量指令。

7. 发明授权

US07818540B2 Vector processing system 有权
标题翻译：矢量处理系统
公开(公告)号：US07818540B2
公开(公告)日：2010-10-19
申请号：US11437385
申请日：2006-05-19
申请人： Stephen Barlow , Neil Bailey , Timothy Ramsdale , David Plowman , Robert Swann
发明人： Stephen Barlow , Neil Bailey , Timothy Ramsdale , David Plowman , Robert Swann
IPC分类号： G06F15/80
CPC分类号： G06F9/30036 , G06F9/3842 , G06F9/3885
摘要： A vector processing system for executing vector instructions, each instruction defining multiple value pairs, an operation to be executed and a modifier, the vector processing system comprising a plurality of parallel processing units, each arranged to receive one of said pairs of values and, when selected, to implement an operation on said value pair to generate a result, each processing unit comprising at least one flag and being selectable in dependence on a condition defined by said at least one flag, wherein the modifier defines the condition under which the parallel processing unit is individually selected.
摘要翻译：用于执行向量指令的矢量处理系统，定义多个值对的每个指令，要执行的操作和修改器，所述向量处理系统包括多个并行处理单元，每个并行处理单元被布置为接收所述一对值中的一个，以及何时被选择以实现对所述值对的操作以产生结果，每个处理单元包括至少一个标志，并且可以根据由所述至少一个标志定义的条件来选择，其中所述修饰符定义所述并行处理的条件单位被单独选择。

8. 发明授权

US07028143B2 Narrow/wide cache 有权
公开(公告)号：US07028143B2
公开(公告)日：2006-04-11
申请号：US10413487
申请日：2003-04-15
申请人： Stephen Barlow , Neil Bailey , Timothy Ramsdale , David Plowman , Robert Swann
发明人： Stephen Barlow , Neil Bailey , Timothy Ramsdale , David Plowman , Robert Swann
IPC分类号： G06F12/02
CPC分类号： G06F9/3828 , G06F9/30145 , G06F9/30167 , G06F9/3885 , G06F9/3889 , G06F12/0804 , G06F12/0888 , Y02D10/13
摘要： A method for transferring data, between a first device and second device in a core processor including a data cache, comprising the steps of, when said first device supports wide data transfer, and said transfer of data comprises a data write operation from said first device to said second device, writing said data to the second device without writing the data to said data cache.

9. 外观设计

USD453095S1 Beverage holder 失效
标题翻译：饮料持有人
公开(公告)号：USD453095S1
公开(公告)日：2002-01-29
申请号：US29136843
申请日：2001-02-08
申请人： Neil Bailey
设计人： Neil Bailey

10. 外观设计

USD408614S Cheese 失效
公开(公告)号：USD408614S
公开(公告)日：1999-04-27
申请号：US69378
申请日：1997-04-09
申请人： Neil Bailey
设计人： Neil Bailey

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