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1. 发明授权

US08375184B2 Mirroring data between redundant storage controllers of a storage system 有权
标题翻译：在存储系统的冗余存储控制器之间镜像数据
公开(公告)号：US08375184B2
公开(公告)日：2013-02-12
申请号：US12627440
申请日：2009-11-30
申请人： Pankaj Kumar , Hang T. Nguyen , Mark Yarch , Timothy J. Jehl , John A. Miller
发明人： Pankaj Kumar , Hang T. Nguyen , Mark Yarch , Timothy J. Jehl , John A. Miller
IPC分类号： G06F12/00
CPC分类号： G06F11/2089 , G06F11/2097
摘要： In one embodiment, the present invention includes canisters to control storage of data in a storage system including a plurality of disks. Each of multiple canisters may have a processor configured for uniprocessor mode and having an internal node identifier to identify the processor and an external node identifier to identify another processor with which it is to mirror cached data. The mirroring of cached data may be performed by communication of non-coherent transactions via the PtP interconnect, wherein the PtP interconnect is according to a cache coherent protocol. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括用于控制包括多个盘的存储系统中的数据存储的罐。多个罐中的每一个可以具有配置成用于单处理器模式并具有内部节点标识符以识别处理器和外部节点标识符的处理器，以识别用于镜像缓存数据的另一个处理器。缓存数据的镜像可以通过经由PtP互连的非相干事务的通信来执行，其中PtP互连是根据高速缓存一致性协议。描述和要求保护其他实施例。

2. 发明申请

US20110131373A1 Mirroring Data Between Redundant Storage Controllers Of A Storage System 有权
标题翻译：在存储系统的冗余存储控制器之间镜像数据
公开(公告)号：US20110131373A1
公开(公告)日：2011-06-02
申请号：US12627440
申请日：2009-11-30
申请人： Pankaj Kumar , Hang T. Nguyen , Mark Yarch , Timothy J. Jehl , John A. Miller
发明人： Pankaj Kumar , Hang T. Nguyen , Mark Yarch , Timothy J. Jehl , John A. Miller
IPC分类号： G06F12/08 , G06F12/00 , G06F12/16
CPC分类号： G06F11/2089 , G06F11/2097
摘要： In one embodiment, the present invention includes canisters to control storage of data in a storage system including a plurality of disks. Each of multiple canisters may have a processor configured for uniprocessor mode and having an internal node identifier to identify the processor and an external node identifier to identify another processor with which it is to mirror cached data. The mirroring of cached data may be performed by communication of non-coherent transactions via the PtP interconnect, wherein the PtP interconnect is according to a cache coherent protocol. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括用于控制包括多个盘的存储系统中的数据存储的罐。多个罐中的每一个可以具有配置成用于单处理器模式并具有内部节点标识符以识别处理器和外部节点标识符的处理器，以识别用于镜像缓存数据的另一个处理器。缓存数据的镜像可以通过经由PtP互连的非相干事务的通信来执行，其中PtP互连是根据高速缓存一致性协议。描述和要求保护其他实施例。

3. 发明授权

US08909862B2 Processing out of order transactions for mirrored subsystems using a cache to track write operations 有权
标题翻译：处理使用高速缓存跟踪写入操作的镜像子系统的顺序事务
公开(公告)号：US08909862B2
公开(公告)日：2014-12-09
申请号：US12495676
申请日：2009-06-30
申请人： Mark A. Yarch , Pankaj Kumar , Hang T. Nguyen
发明人： Mark A. Yarch , Pankaj Kumar , Hang T. Nguyen
IPC分类号： G06F12/08 , G06F11/16 , G06F11/20
CPC分类号： G06F11/1666 , G06F11/20 , G06F2201/82
摘要： Methods and apparatus relating to processing out of order transactions for mirrored subsystems. A first device (that is mirroring data from a second device) includes a cache to track out of order write operations prior to writing data from the write operations to memory. A register may be used to track the state of the cache in response to receipt of a special transaction, which may be a posted transaction or snapshot. The first devise transmits an acknowledgement of commitment of the data to memory once all cache entries, as recorded at a select point by the register, are emptied or otherwise invalidated. Devices may communicate via a peripheral component interconnect express (PCIe) interconnect, and may include a point-to-point or serial link. Various components may be on the same integrated circuit die. An uninterrupted power supply or batteries may supply power in response to a power failure.
摘要翻译：涉及处理镜像子系统的乱序事务的方法和装置。第一设备（即来自第二设备的镜像数据）包括在从写入操作到存储器的数据写入之前跟踪故障写入操作的高速缓存。可以使用寄存器来跟踪高速缓存的状态以响应特殊事务的接收，这可以是已发布的事务或快照。一旦在寄存器的选择点处记录的所有缓存条目被清空或以其他方式被无效，则第一设备将数据承诺的确认传送到存储器。设备可以通过外围组件互连快速（PCIe）互连进行通信，并且可以包括点到点或串行链路。各种组件可以在相同的集成电路管芯上。不间断的电源或电池可能会供电以响应电源故障。

4. 发明申请

US20130185570A1 Providing Per Core Voltage And Frequency Control 审中-公开
公开(公告)号：US20130185570A1
公开(公告)日：2013-07-18
申请号：US13785108
申请日：2013-03-05
申请人： Pankaj Kumar , Hang T. Nguyen , Christopher Houghton , David A. Biermann
发明人： Pankaj Kumar , Hang T. Nguyen , Christopher Houghton , David A. Biermann
IPC分类号： G06F1/26
CPC分类号： G06F1/3296 , G05F1/46 , G06F1/26 , G06F1/3206 , G06F1/3228 , G06F1/324 , G06F9/3016 , Y02D10/126 , Y02D10/172
摘要： In one embodiment, the present invention includes a processor having a plurality of cores and a control logic to control provision of a voltage/frequency to a first core of the plurality of cores independently of provision of a voltage/frequency to at least a second core of the plurality of cores. In some embodiments, the voltages may be provided from one or more internal voltage regulators of the processor. Other embodiments are described and claimed.

5. 发明申请

US20100332756A1 PROCESSING OUT OF ORDER TRANSACTIONS FOR MIRRORED SUBSYSTEMS 有权
标题翻译：处理用于镜像子系统的订单交易
公开(公告)号：US20100332756A1
公开(公告)日：2010-12-30
申请号：US12495676
申请日：2009-06-30
申请人： Mark A. Yarch , Pankaj Kumar , Hang T. Nguyen
发明人： Mark A. Yarch , Pankaj Kumar , Hang T. Nguyen
IPC分类号： G06F12/08 , G06F1/30
CPC分类号： G06F11/1666 , G06F11/20 , G06F2201/82
摘要： Methods and apparatus relating to processing out of order transactions for mirrored subsystems are described. In one embodiment, a device (that is mirroring data from another device) includes a cache to track out of order write operations prior to writing the data from the write operations to memory. A register may be used to track the state of the cache and cause acknowledgement of commitment of the data to memory once all cache entries, as recorded at a select point by the register, are emptied or otherwise invalidated. Other embodiments are also disclosed.
摘要翻译：描述与处理镜像子系统的乱序事务相关的方法和装置。在一个实施例中，在将写入操作的数据写入存储器之前，设备（即来自另一个设备的数据镜像）包括高速缓存以跟踪不合格的写入操作。一旦由寄存器在选择点记录的所有高速缓存条目被清空或以其它方式被无效，则可以使用寄存器来跟踪高速缓存的状态并导致将数据承诺的确认。还公开了其他实施例。

6. 发明申请

US20160182351A1 TECHNOLOGIES FOR NETWORK PACKET CACHE MANAGEMENT 有权
标题翻译：网络包高速缓存管理技术
公开(公告)号：US20160182351A1
公开(公告)日：2016-06-23
申请号：US14580792
申请日：2014-12-23
申请人： Ren Wang , Sameh Gobriel , Christian Maciocco , Tsung-Yuan C. Tai , Ben-Zion Friedman , Hang T. Nguyen , Namakkal N. Venkatesan , Michael A. O'Hanlon , Shrikant M. Shah , Sanjeev Jain
发明人： Ren Wang , Sameh Gobriel , Christian Maciocco , Tsung-Yuan C. Tai , Ben-Zion Friedman , Hang T. Nguyen , Namakkal N. Venkatesan , Michael A. O'Hanlon , Shrikant M. Shah , Sanjeev Jain
IPC分类号： H04L12/757 , H04L12/721 , H04L12/727
CPC分类号： H04L67/2852 , H04L41/0893 , H04L45/38 , H04L45/745 , H04L45/7453 , H04L49/00
摘要： Technologies for identifying a cache line of a network packet for eviction from an on-processor cache of a network device communicatively coupled to a network controller. The network device is configured to determine whether a cache line of the cache corresponding to the network packet is to be evicted from the cache based on a determination that the network packet is not needed subsequent to processing the network packet, and provide an indication that the cache line is to be evicted from the cache based on an eviction policy received from the network controller.
摘要翻译：用于识别网络分组的高速缓存行的技术，用于从通信地耦合到网络控制器的网络设备的处理器上的缓存驱逐。网络设备被配置为基于在处理网络分组之后不需要网络分组的确定来确定与网络分组相对应的高速缓存行是否要从高速缓存中逐出，并提供指示基于从网络控制器接收到的逐出策略，缓存行将从缓存中逐出。

7. 发明授权

US08533401B2 Implementing direct access caches in coherent multiprocessors 有权
标题翻译：在一致的多处理器中实现直接访问缓存
公开(公告)号：US08533401B2
公开(公告)日：2013-09-10
申请号：US10331688
申请日：2002-12-30
申请人： Samantha J. Edirisooriya , Sujat Jamil , David E. Miner , R. Frank O'Bleness , Steven J. Tu , Hang T. Nguyen
发明人： Samantha J. Edirisooriya , Sujat Jamil , David E. Miner , R. Frank O'Bleness , Steven J. Tu , Hang T. Nguyen
IPC分类号： G06F12/00
CPC分类号： G06F12/0831
摘要： Non-processor agents, such as bus agents, may directly access processor caches. A coherency protocol ensures that cache coherency is maintained.
摘要翻译：诸如总线代理的非处理器代理可以直接访问处理器高速缓存。一致性协议确保高速缓存一致性得到维护。

8. 发明授权

US07694080B2 Method and apparatus for providing a low power mode for a processor while maintaining snoop throughput 有权
标题翻译：用于在保持窥探吞吐量的同时为处理器提供低功率模式的方法和装置
公开(公告)号：US07694080B2
公开(公告)日：2010-04-06
申请号：US11027649
申请日：2004-12-29
申请人： Quinn W. Merrell , R. Frank O'Bleness , Sujat Jamil , Hang T. Nguyen
发明人： Quinn W. Merrell , R. Frank O'Bleness , Sujat Jamil , Hang T. Nguyen
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28 , G06F1/26 , G06F1/32 , G06F1/00
CPC分类号： G06F12/0831 , G06F1/3203 , G06F1/324 , G06F2212/1028 , Y02D10/126 , Y02D10/13
摘要： A method and apparatus for providing a low power mode for a processor while maintaining snoop throughput are disclosed. In one embodiment, an apparatus includes a cache, a processor, and a frequency controller. The frequency controller is to operate the apparatus in a low power mode in which the operating frequency of the cache is higher than the operating frequency of the processor.
摘要翻译：公开了一种用于在保持窥探吞吐量的同时为处理器提供低功率模式的方法和装置。在一个实施例中，装置包括高速缓存，处理器和频率控制器。频率控制器将以高功率模式操作该设备，其中高速缓存的工作频率高于处理器的工作频率。

9. 发明授权

US07100001B2 Methods and apparatus for cache intervention 有权
标题翻译：缓存干预的方法和设备
公开(公告)号：US07100001B2
公开(公告)日：2006-08-29
申请号：US10073492
申请日：2002-02-11
申请人： Samantha J. Edirisooriya , Sujat Jamil , David E. Miner , R. Frank O'Bleness , Steven J. Tu , Mark N. Fullerton , Hang T. Nguyen
发明人： Samantha J. Edirisooriya , Sujat Jamil , David E. Miner , R. Frank O'Bleness , Steven J. Tu , Mark N. Fullerton , Hang T. Nguyen
IPC分类号： G06F12/00
CPC分类号： G06F12/0831 , Y02D10/13
摘要： Methods and apparatus for cache-to-cache block transfers (i.e., intervention) when the state of the transferred block is in a non-modified state (e.g., “exclusive” or “shared”) are provided. In one embodiment, a first cache holds the memory block in an “exclusive” state prior to the transfer. When a processor associated with a second cache attempts to read the block from a main memory, the first cache intervenes and supplies the block to the second cache. The state of the block in the first cache changes from “exclusive” to “shared.” In another embodiment, a processor associated with a third cache attempts to read the block from the main memory while the first cache and the second both hold the block in the “shared” state. Either the first cache or the second cache wins an arbitration and supplies the block to the third cache.
摘要翻译：提供了当传送块的状态处于非修改状态（例如，“独占”或“共享”）时用于高速缓存到高速缓存块传送（即干预）的方法和装置。在一个实施例中，第一高速缓存在传输之前将存储块保持在“独占”状态。当与第二高速缓存相关联的处理器尝试从主存储器读取块时，第一缓存介入并将块提供给第二高速缓存。第一个缓存中的块状态从“独占”变为“共享”。在另一个实施例中，与第三高速缓存相关联的处理器尝试从主存储器读取块，而第一高速缓存和第二高速缓冲存储器将第二缓存器保持在“共享”状态。第一缓存或第二高速缓存赢得仲裁，并将块提供给第三高速缓存。

10. 发明授权

US07062613B2 Methods and apparatus for cache intervention 有权
公开(公告)号：US07062613B2
公开(公告)日：2006-06-13
申请号：US11084286
申请日：2005-03-18
申请人： Sujat Jamil , Hang T. Nguyen , Samantha J. Edirisooriya , David E. Miner , R. Frank O'Bleness , Steven J. Tu
发明人： Sujat Jamil , Hang T. Nguyen , Samantha J. Edirisooriya , David E. Miner , R. Frank O'Bleness , Steven J. Tu
IPC分类号： G06F12/06
CPC分类号： G06F12/0831 , Y02D10/13
摘要： Methods and apparatus for cache-to-cache block transfers (i.e., intervention) when the state of the transferred block is in a non-modified state and/or a modified state, without asserting a hit-modified signal line, are provided. In one example, a first cache holds the memory block prior to the transfer. When a processor associated with a second cache attempts to read the block from a main memory, the first cache intervenes and supplies the block to the second cache regardless of the state (modified or non-modified) of the cached block. In addition, an agent associated with the first cache asserts a “hit” signal line regardless of the state (modified or non-modified) of the cached block. The agent associated with the first cache does not assert a “hit-modified” signal line.

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