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1. 发明申请

US20130147511A1 Offline Device Authentication and Anti-Counterfeiting Using Physically Unclonable Functions 审中-公开
标题翻译：使用物理不可克隆功能的离线设备认证和防伪
公开(公告)号：US20130147511A1
公开(公告)日：2013-06-13
申请号：US13313298
申请日：2011-12-07
申请人： Patrick Koeberl , Jiangtao Li , Anand Rajan , Claire Vishik
发明人： Patrick Koeberl , Jiangtao Li , Anand Rajan , Claire Vishik
IPC分类号： H03K19/23
CPC分类号： H03K19/23 , G06F21/73 , H04L9/3263 , H04L9/3278
摘要： The output of a physically unclonable function (PUF) may be processed to reduce its size. The post-processing result is served as a device intrinsic unclonable identifier and is signed by the device manufacturer to create a certificate stored on board the same device that includes the physically unclonable function. This scheme may not require online verification and complex error correction on PUFs in some cases.
摘要翻译：可以处理物理不可克隆功能（PUF）的输出以减小其大小。后处理结果作为设备固有的不可克隆标识符，并由设备制造商签署，以创建存储在同一设备上的证书，其中包含物理上不可克隆的功能。在某些情况下，该方案可能不需要在线验证和PUF复杂的纠错。

2. 发明授权

US09262256B2 Using dark bits to reduce physical unclonable function (PUF) error rate without storing dark bits location 有权
标题翻译：使用暗位来减少物理不可克隆功能（PUF）错误率，而不存储暗位置
公开(公告)号：US09262256B2
公开(公告)日：2016-02-16
申请号：US14140243
申请日：2013-12-24
申请人： Sanu K. Mathew , Sudhir K. Satpathy , Patrick Koeberl , Jiangtao Li , Ram K. Krishnamurthy , Anand Rajan
发明人： Sanu K. Mathew , Sudhir K. Satpathy , Patrick Koeberl , Jiangtao Li , Ram K. Krishnamurthy , Anand Rajan
IPC分类号： G06F21/00 , H04L29/06 , G06F11/07 , G11C7/24 , G11C7/00 , G06F7/58 , H04L9/34
CPC分类号： G06F11/0793 , G06F7/00 , G06F7/588 , G06F11/0745 , G11C7/24 , H04L9/3278 , H04L9/34
摘要： Dark-bit masking technologies for physically unclonable function (PUF) components are described. A computing system includes a processor core and a secure key manager component coupled to the processor core. The secure key manager includes the PUF component, and a dark-bit masking circuit coupled to the PUF component. The dark-bit masking circuit is to measure a PUF value of the PUF component multiple times during a dark-bit window to detect whether the PUF value of the PUF component is a dark bit. The dark bit indicates that the PUF value of the PUF component is unstable during the dark-bit window. The dark-bit masking circuit is to output the PUF value as an output PUF bit of the PUF component when the PUF value is not the dark bit and set the output PUF bit to be a specified value when the PUF value of the PUF component is the dark bit.
摘要翻译：描述了用于物理不可克隆功能（PUF）组件的暗位掩蔽技术。计算系统包括处理器核心和耦合到处理器核心的安全密钥管理器组件。安全密钥管理器包括PUF组件和耦合到PUF组件的暗位屏蔽电路。暗位掩蔽电路是在暗位窗口期间多次测量PUF分量的PUF值，以检测PUF分量的PUF值是否为暗位。暗位表示PUF组件的PUF值在暗位窗口期间不稳定。当PUF值不是暗位时，暗位屏蔽电路将输出PUF值作为PUF分量的输出PUF位，并且当PUF分量的PUF值为黑暗的一点

3. 发明申请

US20150178143A1 USING DARK BITS TO REDUCE PHYSICAL UNCLONABLE FUNCTION (PUF) ERROR RATE WITHOUT STORING DARK BITS LOCATION 有权
标题翻译：使用深色位置减少物理不可靠功能（PUF）错误率，而不会存储明显的位置
公开(公告)号：US20150178143A1
公开(公告)日：2015-06-25
申请号：US14140243
申请日：2013-12-24
申请人： Sanu K. Mathew , Sudhir K. Satpathy , Patrick Koeberl , Jiangtao Li , Ram K. Krishnamurthy , Anand Rajan
发明人： Sanu K. Mathew , Sudhir K. Satpathy , Patrick Koeberl , Jiangtao Li , Ram K. Krishnamurthy , Anand Rajan
IPC分类号： G06F11/07
CPC分类号： G06F11/0793 , G06F7/00 , G06F7/588 , G06F11/0745 , G11C7/24 , H04L9/3278 , H04L9/34
摘要： Dark-bit masking technologies for physically unclonable function (PUF) components are described. A computing system includes a processor core and a secure key manager component coupled to the processor core. The secure key manager includes the PUF component, and a dark-bit masking circuit coupled to the PUF component. The dark-bit masking circuit is to measure a PUF value of the PUF component multiple times during a dark-bit window to detect whether the PUF value of the PUF component is a dark bit. The dark bit indicates that the PUF value of the PUF component is unstable during the dark-bit window. The dark-bit masking circuit is to output the PUF value as an output PUF bit of the PUF component when the PUF value is not the dark bit and set the output PUF bit to be a specified value when the PUF value of the PUF component is the dark bit.
摘要翻译：描述了用于物理不可克隆功能（PUF）组件的暗位掩蔽技术。计算系统包括处理器核心和耦合到处理器核心的安全密钥管理器组件。安全密钥管理器包括PUF组件和耦合到PUF组件的暗位屏蔽电路。暗位掩蔽电路是在暗位窗口期间多次测量PUF分量的PUF值，以检测PUF分量的PUF值是否为暗位。暗位表示PUF组件的PUF值在暗位窗口期间不稳定。当PUF值不是暗位时，暗位屏蔽电路将输出PUF值作为PUF分量的输出PUF位，并且当PUF分量的PUF值为黑暗的一点

4. 发明申请

US20150188717A1 PHYSICALLY UNCLONABLE FUNCTION REDUNDANT BITS 审中-公开
标题翻译：物理上不可逾越的功能冗余位
公开(公告)号：US20150188717A1
公开(公告)日：2015-07-02
申请号：US14141226
申请日：2013-12-26
申请人： Wei WU , Jiangtao Li , Patrick Koeberl
发明人： Wei WU , Jiangtao Li , Patrick Koeberl
IPC分类号： H04L9/32
CPC分类号： H04L9/3278 , G09C1/00 , H03K19/003 , H04L9/0866
摘要： Embodiments of an invention for using physically unclonable function redundant bits are disclosed. In one embodiment, an integrated circuit includes a PUF cell array and redundancy logic. The PUF cell array includes a plurality of redundant cells and is to provide a raw PUF value. The redundancy logic is to generate a redirection list to be used to replace each of one or more bits of the raw PUF value with a redundant bit value from one of the redundant cells.
摘要翻译：公开了用于使用物理上不可克隆的功能冗余位的发明的实施例。在一个实施例中，集成电路包括PUF单元阵列和冗余逻辑。 PUF单元阵列包括多个冗余单元并且提供原始PUF值。冗余逻辑是生成一个重定向列表，用于使用来自冗余单元之一的冗余比特值来替换原始PUF值的一个或多个比特中的每一个。

5. 发明申请

US20140189890A1 DEVICE AUTHENTICATION USING A PHYSICALLY UNCLONABLE FUNCTIONS BASED KEY GENERATION SYSTEM 有权
标题翻译：使用基于物理不可靠函数的密钥生成系统的设备认证
公开(公告)号：US20140189890A1
公开(公告)日：2014-07-03
申请号：US13730469
申请日：2012-12-28
申请人： Patrick Koeberl , Jiangtao Li
发明人： Patrick Koeberl , Jiangtao Li
IPC分类号： G06F21/70
CPC分类号： G06F21/70 , G06F21/44 , G06F21/73 , G09C1/00 , H04L9/0866 , H04L2209/12
摘要： At least one machine accessible medium having instructions stored thereon for authenticating a hardware device is provided. When executed by a processor, the instructions cause the processor to receive two or more device keys from a physically unclonable function (PUF) on the hardware device, generate a device identifier from the two or more device keys, obtain a device certificate from the hardware device, perform a verification of the device identifier, and provide a result of the device identifier verification. In a more specific embodiment, the instructions cause the processor to perform a verification of a digital signature in the device certificate and to provide a result of the digital signature verification. The hardware device may be rejected if at least one of the device identifier verification and the digital signature verification fails.
摘要翻译：提供了至少一个具有存储在其上用于认证硬件设备的指令的机器可访问介质。当处理器执行时，指令使处理器从硬件设备上的物理不可克隆功能（PUF）接收两个或多个设备密钥，从两个或多个设备密钥生成设备标识符，从硬件获得设备证书设备，执行设备标识符的验证，并提供设备标识符验证的结果。在更具体的实施例中，指令使处理器执行设备证书中的数字签名的验证并提供数字签名验证的结果。如果设备标识符验证和数字签名验证中的至少一个失败，则硬件设备可能被拒绝。

6. 发明申请

US20150092939A1 DARK BITS TO REDUCE PHYSICALLY UNCLONABLE FUNCTION ERROR RATES 有权
标题翻译：降低物理不可靠功能错误率的差距
公开(公告)号：US20150092939A1
公开(公告)日：2015-04-02
申请号：US14040337
申请日：2013-09-27
申请人： Kevin Gotze , Gregory Iovino , David Johnston , Patrick Koeberl , Jiangtao Li , Wei Wu
发明人： Kevin Gotze , Gregory Iovino , David Johnston , Patrick Koeberl , Jiangtao Li , Wei Wu
IPC分类号： H04L9/34
CPC分类号： H04L9/34 , G09C1/00 , H04L9/0866 , H04L9/3278 , H04L2209/12
摘要： Embodiments of an invention for using dark bits to reduce physically unclonable function (PUF) error rates are disclosed. In one embodiment, an integrated circuit includes a PUF cell array and dark bit logic. The PUF cell array is to provide a raw PUF value. The dark bit logic is to select PUF cells to mark as dark bits and to generate a dark bit mask based on repeated testing of the PUF cell array.
摘要翻译：公开了使用暗位来减少物理不可克隆功能（PUF）错误率的发明的实施例。在一个实施例中，集成电路包括PUF单元阵列和暗位逻辑。 PUF单元阵列是提供原始PUF值。暗位逻辑是基于PUF单元阵列的重复测试来选择PUF单元来标记为暗位并产生暗位掩码。

7. 发明授权

US09544141B2 Secure key storage using physically unclonable functions 有权
标题翻译：使用物理不可克隆功能保护密钥存储
公开(公告)号：US09544141B2
公开(公告)日：2017-01-10
申请号：US13996544
申请日：2011-12-29
申请人： Jiangtao Li , Anand Rajan , Roel Maes , Sanu K Mathew , Ram Krishnamurthy , Ernie Brickell
发明人： Jiangtao Li , Anand Rajan , Roel Maes , Sanu K Mathew , Ram Krishnamurthy , Ernie Brickell
IPC分类号： H04L29/06 , H04L9/08
CPC分类号： H04L9/0891 , G09C1/00 , H04L9/0822 , H04L9/0861 , H04L9/0866 , H04L9/0894 , H04L2209/12
摘要： Some implementations disclosed herein provide techniques and arrangements for provisioning keys to integrated circuits/processors. A processor may include physically unclonable functions component, which may generate a unique hardware key based at least on at least one physical characteristic of the processor. The hardware key may be employed in encrypting a key such as a secret key. The encrypted key may be stored in a memory of the processor. The encrypted key may be validated. The integrity of the key may be protected by communicatively isolating at least one component of the processor.
摘要翻译：本文公开的一些实施例提供了用于向集成电路/处理器供应密钥的技术和布置。处理器可以包括物理上不可克隆的功能组件，其可以至少基于处理器的至少一个物理特性来生成唯一的硬件密钥。硬件密钥可用于加密诸如秘密密钥的密钥。加密密钥可以存储在处理器的存储器中。可以验证加密的密钥。可以通过通信地隔离处理器的至少一个组件来保护密钥的完整性。

8. 发明申请

US20140189365A1 SECURE KEY DERIVATION AND CRYPTOGRAPHY LOGIC FOR INTEGRATED CIRCUITS 有权
标题翻译：集成电路的安全关键衍生和拼接逻辑
公开(公告)号：US20140189365A1
公开(公告)日：2014-07-03
申请号：US13730829
申请日：2012-12-29
申请人： George W. Cox , David Johnston , Jiangtao Li , Anand Rajan
发明人： George W. Cox , David Johnston , Jiangtao Li , Anand Rajan
IPC分类号： G06F21/72
CPC分类号： G06F21/72 , G06F21/52 , G06F21/73 , G09C1/00 , H04L9/0866 , H04L2209/12
摘要： A processor of an aspect includes root key generation logic to generate a root key. The root key generation logic includes a source of static and entropic bits. The processor also includes key derivation logic coupled with the root key generation logic. The key derivation logic is to derive one or more keys from the root key. The processor also includes cryptographic primitive logic coupled with the root key generation logic. The cryptographic primitive logic is to perform cryptographic operations. The processor also includes a security boundary containing the root key generation logic, the key derivation logic, and the cryptographic primitive logic. Other processors, methods, and systems are also disclosed.
摘要翻译：一方面的处理器包括生成根密钥的根密钥生成逻辑。根密钥生成逻辑包括静态和熵位的源。处理器还包括与根密钥生成逻辑耦合的密钥导出逻辑。密钥推导逻辑是从根密钥导出一个或多个密钥。处理器还包括与根密钥生成逻辑耦合的加密原语逻辑。加密原语逻辑是执行加密操作。处理器还包括包含根密钥生成逻辑，密钥导出逻辑和密码原语逻辑的安全边界。还公开了其他处理器，方法和系统。

9. 发明申请

US20140091832A1 INTEGRATED CIRCUITS HAVING ACCESSIBLE AND INACCESSIBLE PHYSICALLY UNCLONABLE FUNCTIONS 有权
标题翻译：具有可接受和不可接受的物理不可靠功能的集成电路
公开(公告)号：US20140091832A1
公开(公告)日：2014-04-03
申请号：US13631634
申请日：2012-09-28
申请人： Kevin C. Gotze , Gregory M. Iovino , Jiangtao Li , David Johnston , Sanu K. Mathew , George W. Cox , Anand Rajan
发明人： Kevin C. Gotze , Gregory M. Iovino , Jiangtao Li , David Johnston , Sanu K. Mathew , George W. Cox , Anand Rajan
IPC分类号： H03K19/003
CPC分类号： H03K19/003 , G09C1/00 , H04L9/0866 , H04L2209/12
摘要： An integrated circuit substrate of an aspect includes a plurality of exposed electrical contacts. The integrated circuit substrate also includes an inaccessible set of Physically Unclonable Function (PUF) cells to generate an inaccessible set of PUF bits that are not accessible through the exposed electrical contacts. The integrated circuit substrate also includes an accessible set of PUF cells to generate an accessible set of PUF bits that are accessible through the exposed electrical contacts. Other apparatus, methods, and systems are also disclosed.
摘要翻译：一方面的集成电路基板包括多个暴露的电触点。集成电路基板还包括不可接近的物理不可克隆功能（PUF）单元组，以生成不能通过暴露的电触点访问的不可访问的PUF位集合。集成电路基板还包括可访问的PUF单元组，以产生可通过暴露的电触点访问的可访问的PUF位组。还公开了其他装置，方法和系统。

10. 发明申请

US20140201540A1 SECURE KEY STORAGE USING PHYSICALLY UNCLONABLE FUNCTIONS 有权
标题翻译：使用物理不可靠函数确保关键存储
公开(公告)号：US20140201540A1
公开(公告)日：2014-07-17
申请号：US13996544
申请日：2011-12-29
申请人： Jiangtao Li , Anand Rajan , Roel Maes , Sanu K Mathew , Ram Krishnamurthy , Ernie Brickell
发明人： Jiangtao Li , Anand Rajan , Roel Maes , Sanu K Mathew , Ram Krishnamurthy , Ernie Brickell
IPC分类号： H04L9/08
CPC分类号： H04L9/0891 , G09C1/00 , H04L9/0822 , H04L9/0861 , H04L9/0866 , H04L9/0894 , H04L2209/12
摘要： Some implementations disclosed herein provide techniques and arrangements for provisioning keys to integrated circuits/processors. A processor may include physically unclonable functions component, which may generate a unique hardware key based at least on at least one physical characteristic of the processor. The hardware key may be employed in encrypting a key such as a secret key. The encrypted key may be stored in a memory of the processor. The encrypted key may be validated. The integrity of the key may be protected by communicatively isolating at least one component of the processor.
摘要翻译：本文公开的一些实施例提供了用于向集成电路/处理器供应密钥的技术和布置处理器可以包括物理上不可克隆的功能组件，其可以至少基于处理器的至少一个物理特性来生成唯一的硬件密钥。硬件密钥可用于加密诸如秘密密钥的密钥。加密密钥可以存储在处理器的存储器中。可以验证加密的密钥。可以通过通信地隔离处理器的至少一个组件来保护密钥的完整性。

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