专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06933202B1 Method for integrating SiGe NPN and vertical PNP devices on a substrate and related structure 有权
标题翻译：将SiGe NPN和垂直PNP器件集成在衬底和相关结构上的方法
公开(公告)号：US06933202B1
公开(公告)日：2005-08-23
申请号：US10821425
申请日：2004-04-09
申请人： Paul D. Hurwitz , Kenneth M. Ring , Chun Hu , Amol Kalburge
发明人： Paul D. Hurwitz , Kenneth M. Ring , Chun Hu , Amol Kalburge
IPC分类号： H01L21/8228
CPC分类号： H01L21/82285 , H01L21/8228 , H01L27/0826
摘要： According to one exemplary embodiment, a method for forming an NPN and a vertical PNP device on a substrate comprises forming an insulating layer over an NPN region and a PNP region of the substrate. The method further comprises forming a buffer layer on the insulating layer and forming an opening in the buffer layer and the insulating layer in the NPN region, where the opening exposes the substrate. The method further comprises forming a semiconductor layer on the buffer layer and in the opening in the NPN region, where the semiconductor layer has a first portion situated in the opening and a second portion situated on the buffer layer in the PNP region. The first portion of the semiconductor layer forms a single crystal base of the NPN device and the second portion of the semiconductor layer forms a polycrystalline emitter of the vertical PNP device.
摘要翻译：根据一个示例性实施例，在衬底上形成NPN和垂直PNP器件的方法包括在衬底的NPN区域和PNP区域上形成绝缘层。该方法还包括在绝缘层上形成缓冲层，并在NPN区域中的缓冲层和绝缘层中形成开口，其中开口露出基板。所述方法还包括在所述NPN区域中的所述缓冲层和所述开口中形成半导体层，其中所述半导体层具有位于所述开口中的第一部分和位于所述PNP区域中的所述缓冲层上的第二部分。半导体层的第一部分形成NPN器件的单晶基底，半导体层的第二部分形成垂直PNP器件的多晶发射极。

2. 发明授权

US07541231B1 Integration of SiGe NPN and vertical PNP devices on a substrate 有权
标题翻译：将SiGe NPN和垂直PNP器件集成在衬底上
公开(公告)号：US07541231B1
公开(公告)日：2009-06-02
申请号：US11084391
申请日：2005-03-17
申请人： Paul D. Hurwitz , Kenneth M. Ring , Chun Hu , Amol Kalburge
发明人： Paul D. Hurwitz , Kenneth M. Ring , Chun Hu , Amol Kalburge
IPC分类号： H01L21/338 , H01L31/0328 , H01L31/0336 , H01L31/072 , H01L31/109
CPC分类号： H01L21/82285 , H01L21/8228 , H01L27/0826
摘要： According to one exemplary embodiment, a method for forming an NPN and a vertical PNP device on a substrate comprises forming an insulating layer over an NPN region and a PNP region of the substrate. The method further comprises forming a buffer layer on the insulating layer and forming an opening in the buffer layer and the insulating layer in the NPN region, where the opening exposes the substrate. The method further comprises forming a semiconductor layer on the buffer layer and in the opening in the NPN region, where the semiconductor layer has a first portion situated in the opening and a second portion situated on the buffer layer in the PNP region. The first portion of the semiconductor layer forms a single crystal base of the NPN device and the second portion of the semiconductor layer forms a polycrystalline emitter of the vertical PNP device.
摘要翻译：根据一个示例性实施例，在衬底上形成NPN和垂直PNP器件的方法包括在衬底的NPN区域和PNP区域上形成绝缘层。该方法还包括在绝缘层上形成缓冲层，并在NPN区域中的缓冲层和绝缘层中形成开口，其中开口露出基板。所述方法还包括在所述NPN区域中的所述缓冲层和所述开口中形成半导体层，其中所述半导体层具有位于所述开口中的第一部分和位于所述PNP区域中的所述缓冲层上的第二部分。半导体层的第一部分形成NPN器件的单晶基底，半导体层的第二部分形成垂直PNP器件的多晶发射极。

3. 发明授权

US07863148B2 Method for integrating SiGe NPN and vertical PNP devices 有权
标题翻译： SiGe NPN和垂直PNP器件的集成方法
公开(公告)号：US07863148B2
公开(公告)日：2011-01-04
申请号：US12384937
申请日：2009-04-10
申请人： Paul D. Hurwitz , Kenneth M. Ring , Chun Hu , Amol M Kalburge
发明人： Paul D. Hurwitz , Kenneth M. Ring , Chun Hu , Amol M Kalburge
IPC分类号： H01L21/8228 , H01L21/331 , H01L21/8222 , H01L21/8238
CPC分类号： H01L21/82285 , H01L21/8228 , H01L27/0826
摘要： According to one exemplary embodiment, a method for forming an NPN and a vertical PNP device on a substrate comprises forming an insulating layer over an NPN region and a PNP region of the substrate. The method further comprises forming a buffer layer on the insulating layer and forming an opening in the buffer layer and the insulating layer in the NPN region, where the opening exposes the substrate. The method further comprises forming a semiconductor layer on the buffer layer and in the opening in the NPN region, where the semiconductor layer has a first portion situated in the opening and a second portion situated on the buffer layer in the PNP region. The first portion of the semiconductor layer forms a single crystal base of the NPN device and the second portion of the semiconductor layer forms a polycrystalline emitter of the vertical PNP device.
摘要翻译：根据一个示例性实施例，在衬底上形成NPN和垂直PNP器件的方法包括在衬底的NPN区域和PNP区域上形成绝缘层。该方法还包括在绝缘层上形成缓冲层，并在NPN区域中的缓冲层和绝缘层中形成开口，其中开口露出基板。所述方法还包括在所述NPN区域中的所述缓冲层和所述开口中形成半导体层，其中所述半导体层具有位于所述开口中的第一部分和位于所述PNP区域中的所述缓冲层上的第二部分。半导体层的第一部分形成NPN器件的单晶基底，半导体层的第二部分形成垂直PNP器件的多晶发射极。

4. 发明申请

US20090203183A1 Method for integrating SIGE NPN and Vertical PNP Devices 有权
标题翻译：集成SIGE NPN和垂直PNP器件的方法
公开(公告)号：US20090203183A1
公开(公告)日：2009-08-13
申请号：US12384937
申请日：2009-04-10
申请人： Paul D. Hurwitz , Kenneth M. Ring , Chun Hu , Amol M. Kalburge
发明人： Paul D. Hurwitz , Kenneth M. Ring , Chun Hu , Amol M. Kalburge
IPC分类号： H01L21/8228
CPC分类号： H01L21/82285 , H01L21/8228 , H01L27/0826
摘要： According to one exemplary embodiment, a method for forming an NPN and a vertical PNP device on a substrate comprises forming an insulating layer over an NPN region and a PNP region of the substrate. The method further comprises forming a buffer layer on the insulating layer and forming an opening in the buffer layer and the insulating layer in the NPN region, where the opening exposes the substrate. The method further comprises forming a semiconductor layer on the buffer layer and in the opening in the NPN region, where the semiconductor layer has a first portion situated in the opening and a second portion situated on the buffer layer in the PNP region. The first portion of the semiconductor layer forms a single crystal base of the NPN device and the second portion of the semiconductor layer forms a polycrystalline emitter of the vertical PNP device.
摘要翻译：根据一个示例性实施例，在衬底上形成NPN和垂直PNP器件的方法包括在衬底的NPN区域和PNP区域上形成绝缘层。该方法还包括在绝缘层上形成缓冲层，并在NPN区域中的缓冲层和绝缘层中形成开口，其中开口露出基板。所述方法还包括在所述NPN区域中的所述缓冲层和所述开口中形成半导体层，其中所述半导体层具有位于所述开口中的第一部分和位于所述PNP区域中的所述缓冲层上的第二部分。半导体层的第一部分形成NPN器件的单晶基底，半导体层的第二部分形成垂直PNP器件的多晶发射极。

5. 发明授权

US07994611B1 Bipolar transistor fabricated in a biCMOS process 有权
标题翻译：双相晶体管采用biCMOS工艺制造
公开(公告)号：US07994611B1
公开(公告)日：2011-08-09
申请号：US10892015
申请日：2004-07-14
申请人： Kevin Q. Yin , Amol Kalburge , Kenneth M. Ring
发明人： Kevin Q. Yin , Amol Kalburge , Kenneth M. Ring
IPC分类号： H01L29/73
CPC分类号： H01L29/66287 , H01L21/8249 , H01L29/0804 , H01L29/66242
摘要： According to one exemplary embodiment, a bipolar transistor includes a base having a top surface. The bipolar transistor further includes a base oxide layer situated on the top surface of the base. The bipolar transistor further includes an antireflective coating layer situated on the base oxide layer. The bipolar transistor further includes an emitter situated over the top surface of the base and the antireflective coating layer, where a layer of polysilicon is not situated between the base oxide layer and the emitter.
摘要翻译：根据一个示例性实施例，双极晶体管包括具有顶表面的基座。双极晶体管还包括位于基底的顶表面上的基底氧化物层。双极晶体管还包括位于基底氧化物层上的抗反射涂层。双极晶体管还包括位于基极的顶表面和抗反射涂层之上的发射器，其中多晶硅层不位于基底氧化物层和发射极之间。

6. 发明授权

US06797580B1 Method for fabricating a bipolar transistor in a BiCMOS process and related structure 有权
标题翻译： BiCMOS工艺制造双极晶体管及相关结构的方法
公开(公告)号：US06797580B1
公开(公告)日：2004-09-28
申请号：US10371706
申请日：2003-02-21
申请人： Kevin Q. Yin , Amol Kalburge , Kenneth M. Ring
发明人： Kevin Q. Yin , Amol Kalburge , Kenneth M. Ring
IPC分类号： H01L21331
CPC分类号： H01L29/66287 , H01L21/8249 , H01L29/0804 , H01L29/66242
摘要： According to one exemplary embodiment, a method for fabricating a bipolar transistor in a BiCMOS process comprises a step of forming an emitter window stack by sequentially depositing a base oxide layer and an antireflective coating layer on a top surface of a base, where the emitter window stack does not comprise a polysilicon layer. The method further comprises etching an emitter window opening in the emitter window stack. The method further comprises depositing an emitter layer in the emitter window opening and over the antireflective coating layer and etching the emitter layer to form an emitter. The method further comprises etching a first portion of the base oxide layer not covered by the emitter using a first etchant, thereby causing the first portion of the base oxide layer to have a thickness less than a thickness of a second portion of the base oxide layer covered by the emitter.
摘要翻译：根据一个示例性实施例，在BiCMOS工艺中制造双极晶体管的方法包括通过在基底的顶表面上依次沉积基底氧化物层和抗反射涂层来形成发射器窗口叠层的步骤，其中发射极窗口堆叠不包括多晶硅层。该方法还包括蚀刻发射器窗口叠层中的发射器窗口。该方法还包括在发射器窗口和防反射涂层之上沉积发射极层并蚀刻发射极层以形成发射极。该方法还包括使用第一蚀刻剂蚀刻未被发射体覆盖的基底氧化物层的第一部分，从而使得基底氧化物层的第一部分具有小于基底氧化物层的第二部分的厚度的厚度被发射器覆盖。

7. 发明授权

US08497151B2 Photovoltaic device 有权
标题翻译：光伏装置
公开(公告)号：US08497151B2
公开(公告)日：2013-07-30
申请号：US12709858
申请日：2010-02-22
申请人： Gang Xiong , Ricky C. Powell , Aaron Roggelin , Kuntal Kumar , Arnold Allenic , Kenneth M. Ring , Charles Wickersham
发明人： Gang Xiong , Ricky C. Powell , Aaron Roggelin , Kuntal Kumar , Arnold Allenic , Kenneth M. Ring , Charles Wickersham
IPC分类号： H01L21/00
CPC分类号： H01L31/02963 , H01L31/073 , Y02E10/543 , Y02P70/521
摘要： A method to improve CdTe-based photovoltaic device efficiency is disclosed. The CdTe-based photovoltaic device can include oxygen or silicon in semiconductor layers.
摘要翻译：公开了一种改善CdTe基光伏器件效率的方法。 CdTe基光伏器件可以包括半导体层中的氧或硅。

8. 发明申请

US20100288359A1 Photovoltaic Device 有权
标题翻译：光伏器件
公开(公告)号：US20100288359A1
公开(公告)日：2010-11-18
申请号：US12709858
申请日：2010-02-22
申请人： Gang Xiong , Ricky C. Powell , Aaron Roggelin , Kuntal Kumar , Arnold Allenic , Kenneth M. Ring , Charles Wickersham
发明人： Gang Xiong , Ricky C. Powell , Aaron Roggelin , Kuntal Kumar , Arnold Allenic , Kenneth M. Ring , Charles Wickersham
IPC分类号： H01L31/00 , H01L31/0264 , H01L31/0352
CPC分类号： H01L31/02963 , H01L31/073 , Y02E10/543 , Y02P70/521
摘要： A method to improve CdTe-based photovoltaic device efficiency is disclosed. The CdTe-based photovoltaic device can include oxygen or silicon in semiconductor layers.
摘要翻译：公开了一种改善CdTe基光伏器件效率的方法。 CdTe基光伏器件可以包括半导体层中的氧或硅。

9. 发明授权

US07268038B2 Method for fabricating a MIM capacitor having increased capacitance density and related structure 有权
标题翻译：具有增加的电容密度和相关结构的MIM电容器的制造方法
公开(公告)号：US07268038B2
公开(公告)日：2007-09-11
申请号：US10997638
申请日：2004-11-23
申请人： Dieter Dornisch , Kenneth M. Ring , Tinghao F. Wang , David Howard , Guangming Li
发明人： Dieter Dornisch , Kenneth M. Ring , Tinghao F. Wang , David Howard , Guangming Li
IPC分类号： H01L21/8242
CPC分类号： H01L28/40
摘要： According to one embodiment of the invention, a method for fabricating a MIM capacitor in a semiconductor die includes a step of depositing a first interconnect metal layer. The method further includes depositing a layer of silicon nitride on the first interconnect layer. The layer of silicon nitride is deposited in a deposition process using an ammonia-to-silane ratio of at least 12.5. The method further includes depositing a layer of MIM capacitor metal on the layer of silicon nitride. The method further includes etching the layer of MIM capacitor metal to form an upper electrode of the MIM capacitor. According to this exemplary embodiment, the method further includes etching the layer of silicon nitride to form a MIM capacitor dielectric segment and etching the first interconnect metal layer to form a lower electrode of the MIM capacitor. The MIM capacitor has a capacitance density of at least 2.0 fF/um2.
摘要翻译：根据本发明的一个实施例，在半导体管芯中制造MIM电容器的方法包括沉积第一互连金属层的步骤。该方法还包括在第一互连层上沉积氮化硅层。氮化硅层在沉积过程中使用至少12.5的氨 - 硅烷比沉积。该方法还包括在氮化硅层上沉积MIM电容器金属层。该方法还包括蚀刻MIM电容器金属层以形成MIM电容器的上电极。根据该示例性实施例，该方法还包括蚀刻氮化硅层以形成MIM电容器电介质段并蚀刻第一互连金属层以形成MIM电容器的下电极。 MIM电容器具有至少2.0fF / um 2的电容密度。

10. 发明申请

US20130017317A1 LOAD LOCK CONTROL METHOD AND APPARATUS 审中-公开
标题翻译：负载锁定控制方法和装置
公开(公告)号：US20130017317A1
公开(公告)日：2013-01-17
申请号：US13549118
申请日：2012-07-13
申请人： Kenneth M. Ring , Rick C. Powell , William Logan , Feng Liao , Xilin Peng
发明人： Kenneth M. Ring , Rick C. Powell , William Logan , Feng Liao , Xilin Peng
IPC分类号： C23C16/52
CPC分类号： C23C14/566 , C23C16/52
摘要： Method and apparatus for controlling evacuation pressure of a load lock connected to a processing chamber uses prior pressure changes detected in the processing chamber when the load lock communicates with the processing chamber.
摘要翻译：用于控制连接到处理室的负载锁的抽空压力的方法和装置在加载锁与处理室通信时使用在处理室中检测到的先前的压力变化。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式