专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US09882602B2 Global navigation satellite system receiver with filter bypass mode for improved sensitivity 有权
公开(公告)号：US09882602B2
公开(公告)日：2018-01-30
申请号：US13172653
申请日：2011-06-29
申请人： Prasad Srinivasa Siva Gudem , Liang Zhao , I-Hsiang Lin , Zhijie Xiong , Bhushan Shanti Asuri , Aristotele Hadjichristos
发明人： Prasad Srinivasa Siva Gudem , Liang Zhao , I-Hsiang Lin , Zhijie Xiong , Bhushan Shanti Asuri , Aristotele Hadjichristos
IPC分类号： H04B1/3805 , H04B1/525
CPC分类号： H04B1/525 , H04B1/3805
摘要： A global navigation satellite system receiver with filter bypass mode for improved sensitivity is disclosed. In an aspect, an apparatus is provided that includes a non-bypass signal path coupled to a receiver, the non-bypass signal path comprising a filter. The apparatus also includes a bypass signal path coupled to the receiver, the bypass signal path configure to bypass the filter, and a switch to couple an antenna to the non-bypass signal path during time intervals when signals transmitted by an unrelated local transmitter are transmitted with a signal power that exceeds a selected threshold, and to couple the antenna to the bypass signal path during other time intervals.

2. 发明申请

US20130003783A1 GLOBAL NAVIGATION SATELLITE SYSTEM RECEIVER WITH FILTER BYPASS MODE FOR IMPROVED SENSITIVITY 有权
标题翻译：全球导航卫星系统接收器，带有过滤器旁路模式，提高灵敏度
公开(公告)号：US20130003783A1
公开(公告)日：2013-01-03
申请号：US13172653
申请日：2011-06-29
申请人： Prasad Srinivasa Siva Gudem , Liang Zhao , I-Hsiang Lin , Zhijie Xiong , Bhushan Shanti Asuri , Aristotele Hadjichristos
发明人： Prasad Srinivasa Siva Gudem , Liang Zhao , I-Hsiang Lin , Zhijie Xiong , Bhushan Shanti Asuri , Aristotele Hadjichristos
IPC分类号： H04B1/707
CPC分类号： H04B1/525 , H04B1/3805
摘要： A global navigation satellite system receiver with filter bypass mode for improved sensitivity is disclosed. In an aspect, an apparatus is provided that includes a non-bypass signal path coupled to a receiver, the non-bypass signal path comprising a filter. The apparatus also includes a bypass signal path coupled to the receiver, the bypass signal path configure to bypass the filter, and a switch to couple an antenna to the non-bypass signal path during time intervals when signals transmitted by an unrelated local transmitter are transmitted with a signal power that exceeds a selected threshold, and to couple the antenna to the bypass signal path during other time intervals.
摘要翻译：公开了一种具有滤波器旁路模式以提高灵敏度的全球导航卫星系统接收机。在一方面，提供一种装置，其包括耦合到接收器的非旁路信号路径，非旁路信号路径包括滤波器。该装置还包括耦合到接收器的旁路信号路径，配置为旁路滤波器的旁路信号路径以及在由不相关的本地发射机发送的信号被发送的时间间隔期间将天线耦合到非旁路信号路径的开关信号功率超过所选阈值，并且在其它时间间隔期间将天线耦合到旁路信号路径。

3. 发明申请

US20120326792A1 SYSTEMATIC INTERMODULATION DISTORTION CALIBRATION FOR A DIFFERENTIAL LNA 失效
标题翻译：差分LNA的系统互变异常校准
公开(公告)号：US20120326792A1
公开(公告)日：2012-12-27
申请号：US13167655
申请日：2011-06-23
申请人： Cheng-Han Wang , Liang Zhao , Hong Sun Kim , I-Hsiang Lin
发明人： Cheng-Han Wang , Liang Zhao , Hong Sun Kim , I-Hsiang Lin
IPC分类号： H03F1/26 , H03F1/22
CPC分类号： H03F3/193 , H03F1/3211 , H03F3/45188 , H03F2203/45386 , H04B1/1036
摘要： Systematic IM2 calibration for a differential LNA is disclosed. In an aspect, an apparatus includes an amplifier configured to output an amplified signal having a level of systematic pre-mixer IM2 distortion, a detector configured to detect the level of the systematic pre-mixer IM2 distortion in the amplified signal, and a bias signal generator configured to generate at least one bias signal configured to adjust the amplifier to reduce the level of the systematic pre-mixer IM2 distortion.
摘要翻译：公开了用于差分LNA的系统IM2校准。一方面，一种装置包括：放大器，被配置为输出具有系统预混频器IM2失真电平的放大信号;检测器，被配置为检测放大信号中的系统预混频器IM2失真的电平;以及偏置信号配置成产生至少一个偏置信号的发生器，所述至少一个偏置信号被配置为调节放大器以减小系统预混频器IM2失真的电平。

4. 发明授权

US08653892B2 Systematic intermodulation distortion calibration for a differential LNA 失效
标题翻译：差分LNA的系统互调失真校准
公开(公告)号：US08653892B2
公开(公告)日：2014-02-18
申请号：US13167655
申请日：2011-06-23
申请人： Cheng-Han Wang , Liang Zhao , Hong Sun Kim , I-Hsiang Lin
发明人： Cheng-Han Wang , Liang Zhao , Hong Sun Kim , I-Hsiang Lin
IPC分类号： H03F1/26
CPC分类号： H03F3/193 , H03F1/3211 , H03F3/45188 , H03F2203/45386 , H04B1/1036
摘要： Systematic IM2 calibration for a differential LNA is disclosed. In an aspect, an apparatus includes an amplifier configured to output an amplified signal having a level of systematic pre-mixer IM2 distortion, a detector configured to detect the level of the systematic pre-mixer IM2 distortion in the amplified signal, and a bias signal generator configured to generate at least one bias signal configured to adjust the amplifier to reduce the level of the systematic pre-mixer IM2 distortion.
摘要翻译：公开了用于差分LNA的系统IM2校准。一方面，一种装置包括：放大器，被配置为输出具有系统预混频器IM2失真电平的放大信号;检测器，被配置为检测放大信号中的系统预混频器IM2失真的电平;以及偏置信号配置成产生至少一个偏置信号的发生器，所述至少一个偏置信号被配置为调节放大器以减小系统预混频器IM2失真的电平。

5. 发明申请

US20180253657A1 REAL-TIME CREDIT RISK MANAGEMENT SYSTEM 审中-公开
公开(公告)号：US20180253657A1
公开(公告)日：2018-09-06
申请号：US15820340
申请日：2017-11-21
申请人： Liang Zhao , Jiayi Hou
发明人： Liang Zhao , Jiayi Hou
IPC分类号： G06N7/00 , G06N99/00 , G06Q40/02 , G06Q50/00
CPC分类号： G06N7/005 , G06N3/08 , G06N5/003 , G06N20/00 , G06N20/10 , G06N20/20 , G06Q40/025 , G06Q50/01
摘要： The present invention generally relates to a system and method for incorporating computational infrastructure within a statistical learning framework for real-time risk assessment and decision making.

6. 发明授权

US09205466B2 Flow tank 有权
标题翻译：流水箱
公开(公告)号：US09205466B2
公开(公告)日：2015-12-08
申请号：US13989034
申请日：2011-11-23
申请人： Liang Zhao
发明人： Liang Zhao
IPC分类号： B08B3/06 , B08B3/04 , H05K3/26
CPC分类号： B08B3/06 , B08B3/048 , H05K3/26
摘要： A cleaning system comprising a tank having a wash area arranged to receive an article for cleaning; an inlet assembly mounted to a first end of the tank, through which a cleaning medium flows into the wash area; an outlet assembly having a flow control plate mounted to a second end of the tank; the flow control plate having a plurality of apertures and arranged such that the cleaning medium flows from the wash area through the apertures; the flow control plate arranged such that a total outlet area of the tank is equal to a sum of areas of the apertures; wherein the proportion of the total outlet area about the flow control plate is inversely proportional to a depth of the tank.
摘要翻译：一种清洁系统，包括具有布置成接收用于清洁的物品的洗涤区域的罐; 入口组件，其安装到所述罐的第一端，清洁介质通过所述入口组件流入所述洗涤区域; 出口组件，其具有安装到所述罐的第二端的流量控制板; 所述流量控制板具有多个孔，并且被布置成使得所述清洁介质从所述洗涤区域流过所述孔; 所述流量控制板被布置成使得所述罐的总出口面积等于所述孔的面积的总和; 其中围绕流动控制板的总出口面积的比例与罐的深度成反比。

7. 发明申请

US20150324017A1 POSITION INDICATION DEVICE AND POSITION INDICATION METHOD 有权
标题翻译：位置指示装置和位置指示方法
公开(公告)号：US20150324017A1
公开(公告)日：2015-11-12
申请号：US14270720
申请日：2012-05-30
申请人： Liang Zhao
发明人： Liang Zhao
IPC分类号： G06F3/0354 , G06F3/044 , G06F3/046
CPC分类号： G06F3/03545 , G06F3/0418 , G06F3/044 , G06F3/046
摘要： The present invention relates to digital circuit processing and provides a position indication device and a position indication method. In order to improve positioning accuracy of the position indication device without degrading its sensitivity, a position indication device is provided. The device comprises: a voltage dividing circuit connected with a resonant circuit and a rectifying and filtering circuit. The voltage dividing circuit obtains a predetermined proportion of a signal output from the resonant circuit and outputs it to the rectifying and filtering circuit. The present invention is applicable to digital handwriting pens.
摘要翻译：数字电路处理技术领域本发明涉及数字电路处理，提供位置指示装置和位置指示方法。为了提高位置指示装置的定位精度而不降低其灵敏度，提供了位置指示装置。该装置包括：与谐振电路和整流和滤波电路连接的分压电路。分压电路获得从谐振电路输出的信号的预定比例，并将其输出到整流滤波电路。本发明可应用于数字笔迹笔。

8. 发明申请

US20150087114A1 METHOD FOR PACKAGING A POWER DEVICE WITH BOTTOM SOURCE ELECTRODE 有权
标题翻译：用于封装具有底部源电极的功率器件的方法
公开(公告)号：US20150087114A1
公开(公告)日：2015-03-26
申请号：US14033140
申请日：2013-09-20
申请人： Yan Xun Xue , Yueh-Se Ho , Hamza Yilmaz , Jun Lu , Lei Shi , Liang Zhao , Ping Huang
发明人： Yan Xun Xue , Yueh-Se Ho , Hamza Yilmaz , Jun Lu , Lei Shi , Liang Zhao , Ping Huang
IPC分类号： H01L23/495
CPC分类号： H01L23/49537 , H01L23/49541 , H01L23/49548 , H01L23/49551 , H01L23/49562 , H01L23/49575 , H01L2224/16245 , H01L2924/13091 , H01L2924/00
摘要： A power semiconductor package has an ultra thin chip with front side molding to reduce substrate resistance; a lead frame unit with grooves located on both side leads provides precise positioning for connecting numerous bridge-shaped metal clips to the front side of the side leads. The bridge-shaped metal clips are provided with bridge structure and half or fully etched through holes for relieving superfluous solder during manufacturing process.
摘要翻译：功率半导体封装具有超薄芯片，具有正面成型以降低基板电阻; 具有位于两侧引线上的凹槽的引线框单元提供精确的定位，用于将多个桥形金属夹连接到侧引线的前侧。桥形金属夹具有桥结构和半或完全蚀刻的通孔，用于在制造过程中缓解多余的焊料。

9. 发明授权

US08952509B1 Stacked multi-chip bottom source semiconductor device and preparation method thereof 有权
标题翻译：堆叠多芯片底源半导体器件及其制备方法
公开(公告)号：US08952509B1
公开(公告)日：2015-02-10
申请号：US14031283
申请日：2013-09-19
申请人： Hamza Yilmaz , Yueh-Se Ho , Yan Xun Xue , Jun Lu , Xiaotian Zhang , Zhi Qiang Niu , Ming-Chen Lu , Liang Zhao , YuPing Gong , GuoFeng Lian
发明人： Hamza Yilmaz , Yueh-Se Ho , Yan Xun Xue , Jun Lu , Xiaotian Zhang , Zhi Qiang Niu , Ming-Chen Lu , Liang Zhao , YuPing Gong , GuoFeng Lian
IPC分类号： H01L25/07 , H01L23/495 , H01L25/00
CPC分类号： H01L23/49575 , H01L23/3107 , H01L23/49524 , H01L23/49551 , H01L23/49562 , H01L24/37 , H01L24/40 , H01L24/41 , H01L2224/37011 , H01L2224/371 , H01L2224/4007 , H01L2224/40095 , H01L2224/40245 , H01L2224/83801 , H01L2224/84801 , H01L2924/13091 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2924/00014
摘要： The present invention discloses a stacked dual MOSFET package structure and a preparation method thereof. The stacked dual MOSFET package structure comprises a lead frame unit having a die paddle, a first lead and a second lead; a first chip flipped and attached on a top surface of a main paddle of the die paddle; a second chip attached on a bottom surface of the main paddle; and a metal clip mounted on the back of the flipped first chip and electrically connecting an electrode at the back of the first chip to the first lead. A top surface of a metal bump arranged on each electrode at the front of the second chip, a bottom surface of the die pin of the die paddle, a bottom surface of a lead pin of the second lead, and a bottom surface of the first lead are located on the same plane.
摘要翻译：本发明公开了一种叠层双MOSFET封装结构及其制备方法。堆叠双MOSFET封装结构包括具有管芯焊盘，第一引线和第二引线的引线框架单元; 第一芯片翻转并附接在模板的主桨的顶表面上; 附接在主桨的底表面上的第二芯片; 以及安装在翻转的第一芯片的背面上并将第一芯片背面的电极电连接到第一引线的金属夹。布置在第二芯片的前面的每个电极上的金属凸块的顶表面，模板的模具销的底表面，第二引线的引脚的底表面和第一引脚的底表面导线位于同一平面上。

10. 发明授权

US08933518B2 Stacked power semiconductor device using dual lead frame 有权
标题翻译：叠层功率半导体器件采用双引线框架
公开(公告)号：US08933518B2
公开(公告)日：2015-01-13
申请号：US13734201
申请日：2013-01-04
申请人： Yan Xun Xue , Yueh-Se Ho , Lei Shi , Jun Lu , Liang Zhao
发明人： Yan Xun Xue , Yueh-Se Ho , Lei Shi , Jun Lu , Liang Zhao
IPC分类号： H01L23/495 , H01L27/088 , H01L23/00
CPC分类号： H01L23/49575 , H01L23/49524 , H01L23/49537 , H01L23/49562 , H01L24/34 , H01L24/37 , H01L24/40 , H01L24/41 , H01L27/088 , H01L2224/37011 , H01L2224/371 , H01L2224/4007 , H01L2224/40095 , H01L2224/40245 , H01L2224/48091 , H01L2224/48247 , H01L2224/83801 , H01L2224/8385 , H01L2224/84801 , H01L2224/8485 , H01L2924/01322 , H01L2924/13091 , H01L2924/181 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A stacked power semiconductor device includes vertical metal oxide semiconductor field-effect transistors and dual lead frames packaged with flip-chip technology. In the method of manufacturing the stacked power semiconductor device, a first semiconductor chip is flip chip mounted on the first lead frame. A mounting clips is connected to the electrode at back side of the first semiconductor chip. A second semiconductor chip is mounted on the second lead frame, which is then flipped and stacked on the mounting clip.
摘要翻译：叠层功率半导体器件包括垂直金属氧化物半导体场效应晶体管和采用倒装芯片技术封装的双引线框架。在制造堆叠式功率半导体器件的方法中，第一半导体芯片是安装在第一引线框上的倒装芯片。安装夹在第一半导体芯片的背面连接到电极。第二半导体芯片安装在第二引线框架上，然后翻转并堆叠在安装夹上。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式