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    • 1. 发明授权
    • Driving circuit and liquid crystal display using the same
    • 驱动电路和液晶显示器使用相同
    • US08599180B2
    • 2013-12-03
    • US13234097
    • 2011-09-15
    • Qi-Long YuJun ZhangJun-Wei ZhangChia-Hung ChienTsung-Jen ChuangShih-Fang Wong
    • Qi-Long YuJun ZhangJun-Wei ZhangChia-Hung ChienTsung-Jen ChuangShih-Fang Wong
    • G09G5/00
    • G09G3/18G09G2310/0264
    • A driving circuit for driving an LCD includes a common electrode, a number of pixel electrodes, a peripheral circuit, and a processing unit including a first input/output (I/O) port, a second I/O port; and a number of third I/O ports. The first I/O port and the second I/O ports are connected to the common electrode via the peripheral circuit, and each third I/O port is connected to a different pixel electrode. The processing unit controls the first I/O port, the second I/O port, and the third I/O ports to output a first or second voltage according to a display signal, thus the pixel electrodes are at the first or the second voltage accordingly, the common electrode is at a voltage in a range between the second voltage and the first voltage in receiving the voltage output by the peripheral circuit, thus driving the LCD to display an image.
    • 用于驱动LCD的驱动电路包括公共电极,多个像素电极,外围电路和包括第一输入/输出(I / O)端口,第二I / O端口的处理单元; 和多个第三个I / O端口。 第一个I / O端口和第二个I / O端口通过外围电路连接到公共电极,并且每个第三个I / O端口连接到不同的像素电极。 处理单元控制第一I / O端口,第二I / O端口和第三I / O端口,以根据显示信号输出第一或第二电压,因此像素电极处于第一或第二电压 因此,在接收由外围电路输出的电压时,公共电极处于第二电压和第一电压之间的范围内的电压,从而驱动LCD显示图像。
    • 5. 发明授权
    • Charge control system and method
    • 充电控制系统及方法
    • US08468076B2
    • 2013-06-18
    • US13340648
    • 2011-12-29
    • Ho-Leung CheungJia-Lin ChenChun-Wen WangChia-Hung Chien
    • Ho-Leung CheungJia-Lin ChenChun-Wen WangChia-Hung Chien
    • G06Q40/00
    • G06Q20/145G06F1/26G07F15/006H04M15/68H04W4/24
    • A charge control system which is applied in a hardware environment includes an electronic device, an intelligent ammeter, and a server. The intelligent ammeter is connected to the server by a network connection. The charge control system includes a storage unit, and at least one processor. The storage unit stores a plurality of validation information. The at least one processor includes a receiving module, a validating module and a charge control module. The receiving module receives information from a user intended to validate the user. The validating module determines whether the received information matches one of the items of predetermined validation information. The charge control module controls the intelligent ammeter to begin charging the electronic device when the received information matches one of items of the predetermined validation information.
    • 在硬件环境中应用的充电控制系统包括电子设备,智能电表和服务器。 智能电表通过网络连接连接到服务器。 充电控制系统包括存储单元和至少一个处理器。 存储单元存储多个验证信息。 所述至少一个处理器包括接收模块,验证模块和充电控制模块。 接收模块从用户接收旨在验证用户的信息。 验证模块确定所接收的信息是否匹配预定验证信息的项目之一。 当所接收的信息与预定验证信息中的一个项目匹配时,充电控制模块控制智能电表开始对电子设备充电。
    • 6. 发明授权
    • Multicore memory management system
    • 多内存管理系统
    • US07984246B1
    • 2011-07-19
    • US12755893
    • 2010-04-07
    • Geoffrey K. YungChia-Hung Chien
    • Geoffrey K. YungChia-Hung Chien
    • G06F12/00
    • G06F12/0851G06F12/084G06F13/1663G06F2212/1016
    • A multiprocessing system includes, in part, a multitude of processing units each in direct communication with a bus, a multitude of memory units in direct communication with the bus, and at least one shared memory not in direct communication with the bus but directly accessible to the plurality of processing units. The shared memory may be a cache memory that stores instructions and/or data. The shared memory includes a multitude of banks, a first subset of which may store data and a second subset of which may store instructions. A conflict detection block resolves access conflicts to each of the of the banks in accordance with a number of address bits and a predefined arbitration scheme. The conflict detection block provides each of the processing units with sequential access to the banks during consecutive cycles of a clock signal.
    • 多处理系统部分地包括各自与总线直接通信的多个处理单元,与总线直接通信的多个存储器单元,以及至少一个不与总线直接通信但不能直接与总线通信的共享存储器 多个处理单元。 共享存储器可以是存储指令和/或数据的高速缓冲存储器。 共享存储器包括多个存储体,其第一子集可以存储数据,并且其第二子集可以存储指令。 冲突检测块根据多个地址位和预定义的仲裁方案来解决对每个存储体的访问冲突。 冲突检测块在时钟信号的连续周期期间为每个处理单元提供对存储体的顺序访问。
    • 10. 发明授权
    • Multicore memory management system
    • 多内存管理系统
    • US07730261B1
    • 2010-06-01
    • US11507880
    • 2006-08-21
    • Geoffrey K. YungChia-Hung Chien
    • Geoffrey K. YungChia-Hung Chien
    • G06F12/00
    • G06F12/0851G06F12/084G06F13/1663G06F2212/1016
    • A multiprocessing system includes, in part, a multitude of processing units each in direct communication with a bus, a multitude of memory units in direct communication with the bus, and at least one shared memory not in direct communication with the bus but directly accessible to the plurality of processing units. The shared memory may be a cache memory that stores instructions and/or data. The shared memory includes a multitude of banks, a first subset of which may store data and a second subset of which may store instructions. A conflict detection block resolves access conflicts to each of the of the banks in accordance with a number of address bits and a predefined arbitration scheme. The conflict detection block provides each of the processing units with sequential access to the banks during consecutive cycles of a clock signal.
    • 多处理系统部分地包括各自与总线直接通信的多个处理单元,与总线直接通信的多个存储器单元,以及至少一个不与总线直接通信但不能直接与总线通信的共享存储器 多个处理单元。 共享存储器可以是存储指令和/或数据的高速缓冲存储器。 共享存储器包括多个存储体,其第一子集可以存储数据,并且其第二子集可以存储指令。 冲突检测块根据多个地址位和预定义的仲裁方案来解决对每个存储体的访问冲突。 冲突检测块在时钟信号的连续周期期间为每个处理单元提供对存储体的顺序访问。