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1. 外观设计

USD366475S Base for a computer joystick 失效
公开(公告)号：USD366475S
公开(公告)日：1996-01-23
申请号：US31810
申请日：1994-12-06
申请人： Russell Sanchez , Mike Paull , Steve Kaneko , Henry Chin , Robert Dillon , Michael Knodt , Claire Beliard
设计人： Russell Sanchez , Mike Paull , Steve Kaneko , Henry Chin , Robert Dillon , Michael Knodt , Claire Beliard

2. 外观设计

USD366655S Handle for a computer joystick 失效
公开(公告)号：USD366655S
公开(公告)日：1996-01-30
申请号：US31814
申请日：1994-12-06
申请人： Russell Sanchez , Mike Paull , Steve Kaneko , Henry Chin , Robert Dillon , Michael Knodt , Claire Beliard
设计人： Russell Sanchez , Mike Paull , Steve Kaneko , Henry Chin , Robert Dillon , Michael Knodt , Claire Beliard

3. 发明申请

US20110309426A1 Metal Control Gate Structures And Air Gap Isolation In Non-Volatile Memory 有权
标题翻译：金属控制门结构和非易失性存储器中的空气间隙隔离
公开(公告)号：US20110309426A1
公开(公告)日：2011-12-22
申请号：US13163538
申请日：2011-06-17
申请人： Vinod Robert Purayath , Tuan Pham , Hiroyuki Kinoshita , Yuan Zhang , Henry Chin , James K. Kai , Takashi W. Orimoto , George Matamis , Henry Chien
发明人： Vinod Robert Purayath , Tuan Pham , Hiroyuki Kinoshita , Yuan Zhang , Henry Chin , James K. Kai , Takashi W. Orimoto , George Matamis , Henry Chien
IPC分类号： H01L29/788 , H01L21/336 , H01L21/764
CPC分类号： H01L27/11517 , H01L21/28273 , H01L21/764 , H01L21/7682 , H01L27/11519 , H01L27/11521 , H01L29/66825
摘要： High-density semiconductor memory utilizing metal control gate structures and air gap electrical isolation between discrete devices in these types of structures are provided. During gate formation and definition, etching the metal control gate layer(s) is separated from etching the charge storage layer to form protective sidewall spacers along the vertical sidewalls of the metal control gate layer(s). The sidewall spacers encapsulate the metal control gate layer(s) while etching the charge storage material to avoid contamination of the charge storage and tunnel dielectric materials. Electrical isolation is provided, at least in part, by air gaps that are formed in the row direction and/or air gaps that are formed in the column direction.
摘要翻译：提供了利用这些类型结构中的分立器件之间的金属控制栅极结构和气隙电隔离的高密度半导体存储器。在栅极形成和定义期间，蚀刻金属控制栅极层与蚀刻电荷存储层分离，以形成沿着金属控制栅极层的垂直侧壁的保护性侧壁间隔物。侧壁间隔物在蚀刻电荷存储材料时封装金属控制栅极层，以避免电荷存储和隧道介电材料的污染。至少部分地通过在行方向上形成的气隙和/或沿列方向形成的气隙提供电隔离。

4. 发明申请

US20110286265A1 PROGRAMMING NON-VOLATILE STORAGE WITH SYNCHONIZED COUPLING 有权
标题翻译：编程具有同步耦合的非易失性存储
公开(公告)号：US20110286265A1
公开(公告)日：2011-11-24
申请号：US12785636
申请日：2010-05-24
申请人： Nima Mokhlesi , Henry Chin , Masaaki Higashitani
发明人： Nima Mokhlesi , Henry Chin , Masaaki Higashitani
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/10
摘要： A process for programming non-volatile storage is able to achieve faster programming speeds and/or more accurate programming through synchronized coupling of neighboring word lines. The process for programming includes raising voltages for a set of word lines connected a group of connected non-volatile storage elements. The set of word lines include a selected word line, unselected word lines that are adjacent to the selected word line and other unselected word lines. After raising voltages for the set of word lines, the process includes raising the selected word line to a program voltage and raising the unselected word lines that are adjacent to the selected word line to one or more voltage levels concurrently with the raising the selected word line to the program voltage. The program voltage causes at least one of the non-volatile storage elements to experience programming.
摘要翻译：用于编程非易失性存储器的过程能够通过相邻字线的同步耦合来实现更快的编程速度和/或更精确的编程。编程过程包括为连接一组连接的非易失性存储元件的一组字线提升电压。所述字线组包括所选择的字线，与所选字线和其它未选字线相邻的未选字线。在提高该组字线的电压之后，该处理包括将所选择的字线升高到编程电压，并将与所选择的字线相邻的未选字线与提升所选择的字线同时提高到一个或多个电压电平到程序电压。程序电压使至少一个非易失性存储元件经历编程。

5. 发明授权

US07957187B2 Dynamic and adaptive optimization of read compare levels based on memory cell threshold voltage distribution 有权
标题翻译：基于存储单元阈值电压分布的读取比较电平的动态和自适应优化
公开(公告)号：US07957187B2
公开(公告)日：2011-06-07
申请号：US12338850
申请日：2008-12-18
申请人： Nima Mokhlesi , Henry Chin
发明人： Nima Mokhlesi , Henry Chin
IPC分类号： G11C16/04
CPC分类号： G11C11/5642 , G11C16/0483 , G11C29/00
摘要： A process is performed periodically or in response to an error in order to dynamically and adaptively optimize read compare levels based on memory cell threshold voltage distribution. One embodiment of the process includes determining threshold voltage distribution data for a population of non-volatile storage elements, smoothing the threshold voltage distribution data using a weighting function to create an interim set of data, determining a derivative of the interim set of data, and identifying and storing negative to positive zero crossings of the derivative as read compare points.
摘要翻译：周期性地或响应于错误执行过程，以便基于存储器单元阈值电压分布来动态地和自适应地优化读取比较电平。该过程的一个实施例包括确定一组非易失性存储元件的阈值电压分布数据，使用加权函数平滑阈值电压分布数据，以创建临时数据集，确定中间数据集的导数，以及识别和存储导数的正零交叉的负值作为读取的比较点。

6. 发明申请

US20110032757A1 Programming Memory With Reduced Pass Voltage Disturb And Floating Gate-To-Control Gate Leakage 有权
标题翻译：编程存储器具有降低的通过电压干扰和浮动栅极控制栅极泄漏
公开(公告)号：US20110032757A1
公开(公告)日：2011-02-10
申请号：US12536127
申请日：2009-08-05
申请人： Deepanshu Dutta , Henry Chin
发明人： Deepanshu Dutta , Henry Chin
IPC分类号： G11C16/04 , G11C7/10 , G11C16/06
CPC分类号： G11C16/0483 , G11C11/5628 , G11C16/3418 , G11C16/3427
摘要： Program disturb is reduced in a non-volatile storage system by programming storage elements on a selected word line WLn in separate groups, according to the state of their WLn−1 neighbor storage element, and applying an optimal pass voltage to WLn−1 for each group. Initially, the states of the storage elements on WLn−1 are read. A program iteration includes multiple program pulses. A first program pulse is applied to WLn while a first pass voltage is applied to WLn−1, a first group of WLn storage elements is selected for programming, and a second group of WLn storage elements is inhibited. Next, a second program pulse is applied to WLn while a second pass voltage is applied to WLn−1, the second first group of WLn storage elements is selected for programming, and the first group of WLn storage elements is inhibited. A group can include one or more data states.
摘要翻译：根据其WLn-1相邻存储元件的状态，通过在分离的组中对所选字线WLn上的存储元件进行编程来对非易失性存储系统中的程序干扰进行减少，并且对于每一个，向WLn-1施加最佳的通过电压组。最初，读取WLn-1上的存储元件的状态。程序迭代包括多个程序脉冲。当向WLn-1施加第一通过电压时，将第一编程脉冲施加到WLn，选择第一组WLn存储元件进行编程，并且禁止第二组WLn存储元件。接下来，向WLn施加第二编程脉冲，同时将第二通过电压施加到WLn-1，选择第二组WLn存储元件进行编程，并且禁止第一组WLn存储元件。组可以包括一个或多个数据状态。

7. 发明申请

US20080273388A1 ADJUSTING RESISTANCE OF NON-VOLATILE MEMORY USING DUMMY MEMORY CELLS 有权
标题翻译：使用DUMMY MEMORY CELLS调节非易失性记忆电阻
公开(公告)号：US20080273388A1
公开(公告)日：2008-11-06
申请号：US11688874
申请日：2007-03-21
申请人： Henry Chin , Nima Mokhlesi , Dengtao Zhao
发明人： Henry Chin , Nima Mokhlesi , Dengtao Zhao
IPC分类号： G11C11/34
CPC分类号： G11C16/0483 , G11C11/5628 , G11C16/10 , G11C16/3454
摘要： In some non-volatile storage systems, a block of data memory cells is manufactured with a dummy word line at the bottom of the block, at the top of the block, and/or at other locations. By selectively programming memory cells on the dummy word line(s), the resistances associated with the data memory cells can be changed to account for different programmed data patterns.
摘要翻译：在一些非易失性存储系统中，在块的底部，块的顶部和/或其他位置处制造具有伪字线的数据存储单元块。通过选择性地编程虚拟字线上的存储器单元，可以改变与数据存储单元相关联的电阻以考虑不同的编程数据模式。

8. 发明申请

US20080244338A1 Soft bit data transmission for error correction control in non-volatile memory 有权
标题翻译：软比特数据传输用于非易失性存储器中的纠错控制
公开(公告)号：US20080244338A1
公开(公告)日：2008-10-02
申请号：US11694947
申请日：2007-03-31
申请人： Nima Mokhlesi , Henry Chin , Dengtao Zhao
发明人： Nima Mokhlesi , Henry Chin , Dengtao Zhao
IPC分类号： G11C29/00
CPC分类号： G06F11/1068 , G11C2029/0411
摘要： Data stored in non-volatile storage is decoded using iterative probabilistic decoding. An error correcting code such as a low density parity check code may be used. In one approach, initial reliability metrics, such as logarithmic likelihood ratios, are used in decoding sensed states of a set of non-volatile storage element. The decoding attempts to converge by adjusting the reliability metrics for bits in code words which represent the sensed state. Soft data bits are read from the memory if the decoding fails to converge. Initial reliability metric values are provided after receiving the hard read results and at each phase of the soft bit operation(s). In one embodiment, a second soft bit is read from the memory using multiple subsets of soft bit compare levels. While reading at the second subset of compare levels, decoding can be performed based on the first subset data.
摘要翻译：使用迭代概率解码对存储在非易失性存储器中的数据进行解码。可以使用诸如低密度奇偶校验码的纠错码。在一种方法中，初始可靠性度量（诸如对数似然比）被用于解码一组非易失性存储元件的感测状态。解码通过调整表示感测状态的码字中的比特的可靠性度量来尝试收敛。如果解码失败，则从存储器读取软数据位。在接收到硬读取结果之后和在软位操作的每个阶段提供初始可靠性度量值。在一个实施例中，使用软比特比较级的多个子集从存储器读取第二软比特。当在比较级的第二子集读取时，可以基于第一子集数据执行解码。

9. 外观设计

USD449829S1 Audio speaker 失效
标题翻译：音频扬声器
公开(公告)号：USD449829S1
公开(公告)日：2001-10-30
申请号：US29130152
申请日：2000-09-29
申请人： Niklas Gustavsson , David Knaub , Josh Hoyt , Henry Chin
设计人： Niklas Gustavsson , David Knaub , Josh Hoyt , Henry Chin

10. 发明授权

US06076127A Configuration of a single point bus arbitration scheme using on-chip arbiters 失效
标题翻译：使用片上仲裁器配置单点总线仲裁方案
公开(公告)号：US06076127A
公开(公告)日：2000-06-13
申请号：US744812
申请日：1996-11-06
申请人： Henry Chin , George Totolos, Jr.
发明人： Henry Chin , George Totolos, Jr.
IPC分类号： G06F13/364 , B41B15/00 , G06F13/00 , G06F13/40 , G06F13/42
CPC分类号： G06F13/364
摘要： A method and apparatus for configuring a single point arbitration scheme for a commonly accessed communication bus using bus master devices with arbitration control circuitry included therein. Bus master devices including arbitration control circuitry may be connected to an arbitration control bus over which signals for arbitrating control to the commonly accessed communications bus are provided. During a configuration mode of operation, the same connections to the arbitration control bus provide signals which are decoded at each bus master device to provide a configuration status which indicates whether other bus master devices requiring arbitration are connected to the arbitration control bus and whether the arbitration control circuitry included on the particular device will be enabled to perform the arbitration. Accordingly, single point arbitration of a commonly accessed bus is configured without adding an external arbiter circuit to the bus system or otherwise increasing the I/O requirements of the bus master devices.
摘要翻译：一种用于使用其中包括仲裁控制电路的总线主设备来配置用于共同访问的通信总线的单点仲裁方案的方法和装置。包括仲裁控制电路的总线主设备可以连接到仲裁控制总线，通过该仲裁控制总线提供用于仲裁控制到共同访问的通信总线的信号。在配置操作模式下，与仲裁控制总线的相同连接提供在每个总线主设备处解码的信号，以提供配置状态，该配置状态指示需要仲裁的其他总线主设备是否连接到仲裁控制总线以及是否仲裁包括在特定设备上的控制电路将被执行仲裁。因此，配置普通访问总线的单点仲裁，而不需要向总线系统添加外部仲裁器电路，或以其他方式增加总线主器件的I / O要求。

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