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1. 发明公开

KR20200145948A 반도체 소자 및 반도체 소자의 제조방법 审中-公开
公开(公告)号：KR20200145948A
公开(公告)日：2020-12-31
申请号：KR20190074082
申请日：2019-06-21
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： PARK HYE SUNG , BAE JIN WOO , KOH YOUNG HO , PARK JONG HYUK , YOON BO UN , JANG MYUNG JAE
IPC分类号： H01L21/8234 , H01L21/768 , H01L27/088
摘要： 본개시의일 실시예는, 셀영역과주변영역을포함하는기판과, 상기셀 영역상에배치된셀 게이트구조물과, 상기셀 게이트구조물의양측의상기셀 영역내에배치된제1 불순물영역및 제2 불순물영역과, 상기셀 게이트구조물상에배치되며, 상기셀 게이트구조물과교차하고, 상기제1 불순물영역에연결된비트라인구조물과, 상기주변영역상에배치된주변게이트구조물과, 상기주변영역상에배치되며, 상기주변게이트구조물을덮고, 상기비트라인구조물의상단과실질적으로동일한레벨의상면을갖는주변캐핑층과, 상기제2 불순물영역상에배치되며, 도전성배리어와상기도전성배리어상의콘택물질층을가지고, 상기도전성배리어는상기비트라인구조물의상단을덮는셀 콘택구조물을포함하는반도체소자를제공한다.

2. 发明授权

KR100733140B1 METHOD OF FORMING AN ETCHING MASK 无效
标题翻译：形成蚀刻掩模的方法
公开(公告)号：KR100733140B1
公开(公告)日：2007-06-21
申请号：KR20060053013
申请日：2006-06-13
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： YUN SE RAH , HONG CHANG KI , YOON BO UN , LEE JONG WON
IPC分类号： H01L21/027
CPC分类号： H01L21/0337 , H01L21/0338 , H01L21/31051
摘要： A method for forming an etch mask is provided to obtain ultra-fine line/space patterns by forming a plurality of spacers using two materials with different etch selectivity. A pre-pattern(204) containing a first material is formed on a substrate(200). A first spacer(208) is formed at both sidewalls of the pre-pattern. The first spacer contains a second material with a relatively different etch selectivity compared to the first material. The width of the first spacer is the same as that of the pre-pattern. A second spacer(210) is formed at each sidewalls of the first spacer. The second spacer contains the first material. The width of the second spacer is the same as that of the pre-pattern. A third spacer(212) is formed at each sidewall of the second spacer. The third spacer contains a second material. The width of the third spacer is the same as that of the pre-pattern. A thin film(214) containing the first material is formed on the resultant structure.
摘要翻译：提供一种用于形成蚀刻掩模的方法，以通过使用具有不同蚀刻选择性的两种材料形成多个间隔物来获得超细线/间隔图案。在基板（200）上形成包含第一材料的预图案（204）。在预图案的两个侧壁处形成第一间隔物（208）。第一间隔物含有与第一材料相比具有相对不同蚀刻选择性的第二材料。第一间隔物的宽度与预图案的宽度相同。第二间隔件（210）形成在第一间隔件的每个侧壁处。第二间隔物包含第一材料。第二间隔物的宽度与预图案的宽度相同。第三间隔件（212）形成在第二间隔件的每个侧壁处。第三间隔物包含第二材料。第三间隔物的宽度与预图案的宽度相同。在所得结构上形成含有第一材料的薄膜（214）。

3. 发明公开

KR20180066383A 반도체 장치 및 그 제조 방법 审中-公开
公开(公告)号：KR20180066383A
公开(公告)日：2018-06-19
申请号：KR20160166910
申请日：2016-12-08
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： PYON YOUNG BEOM , PARK KI CHUL , KIM IN KWON , JANG KI HOON , KWON BYOUNG HO , KIM SANG KYUN , YOON BO UN
IPC分类号： H01L27/115
CPC分类号： H01L23/528 , H01L23/535 , H01L27/112 , H01L27/11551 , H01L27/11578
摘要： 반도체장치및 그제조방법이제공된다. 반도체장치는주변회로영역및 셀어레이영역을포함하는기판, 상기주변회로영역상의주변구조체, 상기주변회로영역및 상기셀 어레이영역을덮는하부절연막, 상기주변회로영역상의상기하부절연막은평탄부및 상기평탄부로부터돌출된돌출부를갖는것, 및상기셀 어레이영역상의상기하부절연막상에배치되는적층구조체를포함한다. 상기적층구조체는교대로그리고반복적으로적층된도전패턴들및 절연패턴들을포함한다.

4. 发明公开

KR20100030125A Photo key and fabrication method of semiconductor device using the same 有权
标题翻译：使用其的半导体器件的照相键和制造方法
公开(公告)号：KR20100030125A
公开(公告)日：2010-03-18
申请号：KR20080088918
申请日：2008-09-09
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： KWON BYOUNG HO , HONG CHANG KI , YOON BO UN , LEE JAE DONG , KIM SANG JIN
IPC分类号： H01L21/027
CPC分类号： H01L23/544 , G03F7/70633 , G03F9/7076 , H01L2223/54453 , H01L2924/0002 , G03F9/708 , H01L2924/00
摘要： PURPOSE: A photo key and a method for manufacturing a semiconductor device using the same are provided to prevent the height of photo key regions from reducing while the photo key regions are chemically and mechanically grinded by inserting conductive patterns in the photo key regions. CONSTITUTION: Photo key regions(12), first conductive patterns(18) and a second conductive pattern(20) are prepared. The photo key regions are formed to be spaced apart on a semiconductor substrate(10). The first conductive pattern is formed to be spaced apart in one photo key region. The second conductive pattern is formed between and around the first conductive patterns.
摘要翻译：目的：提供一种照相钥匙和使用其的制造半导体器件的方法，以通过在光密钥区域中插入导电图案来化学和机械地研磨光键区域，防止光键区域的高度减小。构成：制备光键区域（12），第一导电图案（18）和第二导电图案（20）。光密钥区域形成为在半导体衬底（10）上间隔开。第一导电图案形成为在一个照片键区域中间隔开。在第一导电图案之间和周围形成第二导电图案。

5. 发明公开

KR20180066940A 반도체 소자의 제조 방법 审中-公开
公开(公告)号：KR20180066940A
公开(公告)日：2018-06-20
申请号：KR20160167856
申请日：2016-12-09
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： BAE KI HO , KIM JAE SEOK , KIM HO YOUNG , YOON BO UN , LEE KYUNG TAE , KIM KWAN SUNG , PARK EUN JI
IPC分类号： H01L29/78 , H01L21/02 , H01L21/033 , H01L21/311 , H01L21/8234
CPC分类号： H01L21/823475 , H01L21/823418 , H01L21/823437
摘要： 본발명은반도체소자의제조방법에관한것으로, 더욱상세하게는, 기판상에서로인접하는제1 내지제4 게이트전극들을형성하는것, 상기제1 내지제4 게이트전극들은제1 방향으로연장되고, 상기제1 내지제4 게이트전극들은제1 방향과교차하는제2 방향으로배열되며; 상기제1 내지제4 게이트전극들상에제1 내지제4 캡핑패턴들을각각형성하는것; 상기제1 내지제4 게이트전극들사이의공간들을채우는층간절연막을형성하는것; 상기층간절연막상에하드마스크패턴을형성하는것, 상기하드마스크패턴은상기제2 내지제4 캡핑패턴들을선택적으로노출하는개구부를갖고; 상기하드마스크패턴을식각마스크로상기제2 및제3 게이트전극들사이및 상기제3 및제4 게이트전극들사이의상기층간절연막을식각하여, 홀들을형성하는것; 상기홀들을채우는배리어막및 도전막을순차적으로형성하는것; 상기하드마스크패턴이노출될때까지제1 평탄화공정을수행하는것; 상기제2 내지제4 캡핑패턴들을덮는상기배리어막의일부가노출될때까지제2 평탄화공정을수행하는것; 및상기제1 내지제4 캡핑패턴들이완전히노출될때까지제3 평탄화공정을수행하는것을포함한다.

6. 发明公开

KR20070108685A SLURRY RECYLING SYSTEM, SLURRY SEGREGATING SYSTEM AND SLURRY RECYCLING METHOD 审中-公开
标题翻译：浆液回收系统，浆料分离系统和浆液循环方法
公开(公告)号：KR20070108685A
公开(公告)日：2007-11-13
申请号：KR20060041036
申请日：2006-05-08
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： KIM SUNG JUN , HONG CHANG KI , YOON BO UN
IPC分类号： B24B57/00 , B24B37/00 , H01L21/304
CPC分类号： B24B57/00 , H01L21/304
摘要： A slurry recycling system, a slurry segregating system and a slurry recycling method are provided to reduce cost for a CMP(Chemical Mechanical Planarization) process by performing the CMP process stably using recycled slurry without damaging a wafer. A slurry recycling system comprises a slurry collecting unit(120), a slurry segregating unit(130), an abrasive particle filtering unit(140), a chemical filtering unit(150), and a mixing unit(160). The slurry segregating unit segregates abrasive particles from chemicals using an electric field including a plus electrode and a minus electrode. A slurry recycling method includes the steps of: collecting slurry; segregating the slurry to get the abrasive particles and the chemicals; filtering the abrasive particles; filtering the chemicals; and mixing the abrasive particles with the chemicals again.
摘要翻译：提供浆料循环系统，浆料分离系统和浆料回收方法，以通过使用再循环浆料稳定地进行CMP工艺来降低CMP（化学机械平面化）工艺的成本，而不损坏晶片。浆料循环系统包括浆料收集单元（120），浆料分离单元（130），磨料颗粒过滤单元（140），化学过滤单元（150）和混合单元（160）。浆料分离单元使用包括正电极和负电极的电场将磨料颗粒与化学品分离。浆料回收方法包括以下步骤：收集浆料; 分离浆料以得到磨料颗粒和化学品; 过滤磨料颗粒; 过滤化学品; 并再次将磨料颗粒与化学品混合。

7. 发明公开

KR20200143144A 슬러리 조성물 및 이를 이용한 집적회로 소자의 제조 방법 审中-公开
公开(公告)号：KR20200143144A
公开(公告)日：2020-12-23
申请号：KR20190071069
申请日：2019-06-14
申请人： SAMSUNG ELECTRONICS CO LTD , SEOUL NAT UNIV R&DB FOUNDATION
发明人： JEON YE RYUNG , KIM BO YUN , CHUNG TAEK DONG , YOON BO UN , LEE JAE GYEONG , LEE JIN YOUNG
IPC分类号： C09G1/02 , C09K3/14 , C23F3/04 , C23F11/18 , H01L21/304 , H01L21/321 , H01L21/768
摘要： 슬러리조성물은탄소동소체및 그유도체로부터선택되는물질로이루어지는부식방지제와, 산화제를포함한다. 집적회로소자의제조방법에서는기판상에서로다른금속을포함하는제1 금속막및 제2 금속막을형성하고, 상기제1 금속막및 상기제2 금속막이노출된연마대상면을상기슬러리조성물을이용하여연마한다.

8. 发明公开

KR20070103921A METHOD OF FABRICATING SEMICONDUCTOR DEVICE 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：KR20070103921A
公开(公告)日：2007-10-25
申请号：KR20060035844
申请日：2006-04-20
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： YUN SEONG KYU , HONG CHANG KI , YOON BO UN , KIM HO YOUNG , LIM JOUNG HEUN , HAN SANG YEOB
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/66795 , H01L21/76224 , H01L29/785
摘要： A method for fabricating a semiconductor device is provided to suppress the increase of electric potential in electrically independent active pins by an electric field generated by gate patterns. A method for fabricating a semiconductor device includes the steps of: forming a hard mask on a substrate; forming a device isolation trench to define a plurality of active pins(115a) arranged in two dimensions by etching the substrate using the hard mask as an etch mask; forming a device isolation layer(130) filling a space between the device isolation trench and the hard masks; forming a plurality of holes between the active pins by patterning the device isolation layer; forming a plurality of recesses to expose the side walls of the active pins between the buried patterns and the active pins; and forming a plurality of gate patterns filling the recesses and crossing the active pins along a second direction.
摘要翻译：提供一种用于制造半导体器件的方法，以通过栅极图案产生的电场来抑制电独立的有效引脚中的电位的增加。一种制造半导体器件的方法包括以下步骤：在衬底上形成硬掩模; 形成器件隔离沟槽以限定通过使用所述硬掩模作为蚀刻掩模蚀刻所述衬底而在二维中排列的多个有源引脚（115a）形成填充所述器件隔离沟槽和所述硬掩模之间的空间的器件隔离层（130）; 通过图案化所述器件隔离层在所述有源引脚之间形成多个孔; 形成多个凹部以暴露所述有源销在所述掩埋图案和所述有源销之间的侧壁; 以及形成填充所述凹部并沿着第二方向与所述活动销交叉的多个栅极图案。

9. 发明公开

KR20070092456A SEMICONDUCTOR DEVICE HAVING RESISTOR PATTERN AND METHOD OF FABRICATING THE SAME 审中-公开
标题翻译：具有电阻图案的半导体器件及其制造方法
公开(公告)号：KR20070092456A
公开(公告)日：2007-09-13
申请号：KR20060022614
申请日：2006-03-10
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： KWON BYOUNG HO , HONG CHANG KI , YOON BO UN , CHOI JAE KWANG , KIM CHAE LYOUNG
IPC分类号： H01L27/115 , H01L21/8247
CPC分类号： H01L21/76838 , H01L21/3205
摘要： A semiconductor device is provided to skip a planarization process of a first interlayer dielectric by designing conductive patterns and a resistance pattern in a manner that the conductive patterns don't overlap the resistance pattern. A conductive pattern(35) is disposed in the first region of a semiconductor substrate having first and second regions(R1,R2). The conductive pattern and the semiconductor substrate are covered with a first interlayer dielectric. The fist interlayer dielectric is disposed in a manner that the upper surface of the conductive pattern has a higher level than the upper surface of the semiconductor substrate. A resistance pattern(45) is disposed on the first interlayer dielectric in the second region. The resistance pattern and the first interlayer dielectric are covered with a second planarized interlayer dielectric. A low-k dielectric layer and a capping layer can be sequentially stacked in the first interlayer dielectric.
摘要翻译：提供半导体器件以通过以导电图案不与电阻图案重叠的方式设计导电图案和电阻图案来跳过第一层间电介质的平坦化处理。导电图案（35）设置在具有第一和第二区域（R1，R2）的半导体衬底的第一区域中。导电图案和半导体衬底被第一层间电介质覆盖。第一层间电介质以使得导电图案的上表面具有比半导体衬底的上表面更高的水平的方式设置。电阻图案（45）设置在第二区域中的第一层间电介质上。电阻图案和第一层间电介质用第二平面化层间电介质覆盖。低k电介质层和覆盖层可以顺序堆叠在第一层间电介质中。

10. 发明公开

KR20070078929A METHOD FOR FABRICATING FLASH MEMORY DEVICE 审中-公开
标题翻译：用于制造闪速存储器件的方法
公开(公告)号：KR20070078929A
公开(公告)日：2007-08-03
申请号：KR20060009376
申请日：2006-01-31
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： YUN SE RAH , LEE JONG WON , YOON BO UN , HONG CHANG KI
IPC分类号： H01L27/115 , H01L21/76 , H01L21/8247
CPC分类号： H01L27/11521 , H01L21/76224 , H01L21/76838
摘要： A method for fabricating a flash memory device is provided to simplify a manufacturing process and increase productivity by using a sacrificial polymer as a sacrificial layer. A cell region and core/periphery regions(112,114,116) are defined on a semiconductor substrate(100). A tunnel insulating layer and a first conductive layer pattern(120) are formed on the semiconductor substrate. A trench is formed within the semiconductor substrate by using the first conductive layer pattern as an etch mask. An isolation layer(102) is formed to fill up the trench and the first conductive layer pattern. The first conductive layer pattern of the cell region is eliminated. A second conductive layer pattern(122) is conformally formed on the tunnel insulating layer of the cell region and a side of the isolation layer. An intergate insulating layer(140) and a third conductive layer pattern are formed on the first and second conductive layer patterns. A control gate(150) and a floating gate are formed by patterning the third conductive layer, the intergate insulating layer, and the first and second conductive layer patterns.
摘要翻译：提供了一种用于制造闪速存储器件的方法，以简化制造工艺并通过使用牺牲聚合物作为牺牲层来提高生产率。单元区域和芯/外围区域（112,114,116）被限定在半导体衬底（100）上。隧道绝缘层和第一导电层图案（120）形成在半导体衬底上。通过使用第一导电层图案作为蚀刻掩模，在半导体衬底内形成沟槽。形成隔离层（102）以填充沟槽和第一导电层图案。消除了单元区域的第一导电层图案。第二导电层图案（122）共形地形成在电池区域的隧道绝缘层和隔离层的一侧上。在第一和第二导电层图案上形成间隔绝缘层（140）和第三导电层图案。通过图案化第三导电层，隔间绝缘层以及第一和第二导电层图案来形成控制栅极（150）和浮置栅极。

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