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1. 发明申请

US20060019478A1 Silicide method for CMOS integrated circuits 有权
公开(公告)号：US20060019478A1
公开(公告)日：2006-01-26
申请号：US10896599
申请日：2004-07-21
申请人： Song Zhao , Sue Crank , Amitava Chatterjee , Kaiping Liu , Jiong-Ping Lu , Donald Miles , Duofeng Yue , Lance Robertson
发明人： Song Zhao , Sue Crank , Amitava Chatterjee , Kaiping Liu , Jiong-Ping Lu , Donald Miles , Duofeng Yue , Lance Robertson
IPC分类号： H01L21/28
CPC分类号： H01L21/823814 , H01L21/26506 , H01L21/28518 , H01L21/823835 , H01L29/665
摘要： A method for forming metal silicide regions in source and drain regions (160, 170) is described. Prior to the thermal annealing of the source and drain regions (160, 170), germanium is implanted into a semiconductor substrate adjacent to sidewall structures (90, 95) formed adjacent gate structures (60, 70). The position of the implanted germanium species in the semiconductor substrate will overlap the source and drain regions (160, 170). Following thermal annealing of the source and drain regions (160, 170), the implanted germanium prevents the formation of metal silicide spikes.

2. 发明申请

US20050208764A1 Integrated circuit metal silicide method 有权
标题翻译：集成电路金属硅化物法
公开(公告)号：US20050208764A1
公开(公告)日：2005-09-22
申请号：US11073982
申请日：2005-03-07
申请人： Jiong-Ping Lu , Duofeng Yue , Xiaozhan Liu , Donald Miles , Lance Robertson
发明人： Jiong-Ping Lu , Duofeng Yue , Xiaozhan Liu , Donald Miles , Lance Robertson
IPC分类号： H01L21/265 , H01L21/285 , H01L21/336 , H01L21/44 , H01L21/4763 , H01L29/78
CPC分类号： H01L29/665 , H01L21/26506 , H01L21/28518 , H01L29/7833
摘要： Fluorine containing regions (70) are formed in the source and drain regions (60) of the MOS transistor. A metal layer (90) is formed over the fluorine containing regions (70) and the source and drain regions (60). The metal layer is reacted with the underlying fluorine containing regions to form a metal silicide.
摘要翻译：含氟区域（70）形成在MOS晶体管的源区和漏区（60）中。在含氟区域（70）和源极和漏极区域（60）之上形成金属层（90）。金属层与下面的含氟区域反应以形成金属硅化物。

3. 发明申请

US20060258091A1 Novel method for manufacturing a semiconductor device containing metal silicide regions 有权
标题翻译：用于制造包含金属硅化物区域的半导体器件的新方法
公开(公告)号：US20060258091A1
公开(公告)日：2006-11-16
申请号：US11127669
申请日：2005-05-12
申请人： Juanita DeLoach , Lindsey Hall , Lance Robertson , Jiong-Ping Lu , Donald Miles
发明人： Juanita DeLoach , Lindsey Hall , Lance Robertson , Jiong-Ping Lu , Donald Miles
IPC分类号： H01L21/336
CPC分类号： H01L21/28052 , H01L21/28518 , H01L29/665
摘要： The present invention provides a method for manufacturing a semiconductor device. In one embodiment of the present invention, without limitation, the method for manufacturing the semiconductor device includes forming a gate structure (120) over a substrate (110) and forming source/drain regions (190) in the substrate (110) proximate the gate structure (120). The method further includes forming fluorine containing regions (220) in the source/drain regions (190) employing a fluorine containing plasma using a power level of less than about 75 Watts, forming a metal layer (310) over the substrate (110) and fluorine containing regions (220), and reacting the metal layer (310) with the fluorine containing regions (220) to form metal silicide regions (410) in the source/drain regions (190).
摘要翻译：本发明提供一种制造半导体器件的方法。在本发明的一个实施例中，但不限于，用于制造半导体器件的方法包括在衬底（110）上形成栅极结构（120）并且在靠近栅极的衬底（110）中形成源/漏区（190）结构（120）。该方法还包括在源极/漏极区（190）中使用含氟等离子体，使用小于约75瓦特的功率电平形成含氟区域（220），在基底（110）上形成金属层（310），以及含氟区域（220），并且使金属层（310）与含氟区域（220）反应以在源极/漏极区域（190）中形成金属硅化物区域（410）。

4. 发明申请

US20060014387A1 Silicide formation using a low temperature anneal process 有权
标题翻译：使用低温退火工艺的硅化物形成
公开(公告)号：US20060014387A1
公开(公告)日：2006-01-19
申请号：US11155151
申请日：2005-06-17
申请人： Lance Robertson , Jiong-Ping Lu , Donald Miles
发明人： Lance Robertson , Jiong-Ping Lu , Donald Miles
IPC分类号： H01L21/44
CPC分类号： H01L27/0629 , H01L21/28518 , H01L28/24 , H01L29/7833
摘要： A silicide 160 is formed in exposed silicon on a semiconductor wafer 10 by a method that includes forming a thin interface layer 140 over the semiconductor wafer 10 and performing a first low temperature anneal to create the silicide 160. The method further includes removing an unreacted portion of the interface layer 140 and performing a second low temperature anneal to complete the formation of a low resistance silicide 160.
摘要翻译：硅化物160通过包括在半导体晶片10上形成薄界面层140并进行第一低温退火以形成硅化物160的方法在半导体晶片10的暴露硅中形成。该方法还包括去除未反应部分并执行第二低温退火以完成低电阻硅化物160的形成。

5. 发明申请

US20060121706A1 Divergent charged particle implantation for improved transistor symmetry 有权
标题翻译：用于改善晶体管对称性的发散带电粒子注入
公开(公告)号：US20060121706A1
公开(公告)日：2006-06-08
申请号：US11006185
申请日：2004-12-07
申请人： James Bernstein , Lance Robertson , Said Ghneim , Jiejie Xu , Jeffrey Loewecke
发明人： James Bernstein , Lance Robertson , Said Ghneim , Jiejie Xu , Jeffrey Loewecke
IPC分类号： H01L21/425
CPC分类号： H01L29/78 , H01J2237/31701 , H01L21/26513 , H01L29/66575
摘要： The present invention provides a method for implanting charged particles in a substrate and a method for manufacturing an integrated circuit. The method for implanting charged particles in a substrate, among other steps, includes projecting a beam of charged particles (320) to a substrate (330), the beam of charged particles (320) having a given beam divergence, and forming a diverged beam of charged particles (360) by subjecting the beam of charged particles (320) to an energy field (350), thereby causing the beam of charged particles (320) to have a larger beam divergence. The method then desires implanting the diverged beam of charged particles (360) into the substrate (330).
摘要翻译：本发明提供了一种用于将带电粒子注入基板的方法和用于制造集成电路的方法。用于将带电粒子注入衬底的方法以及其他步骤包括将带电粒子束（320）投射到衬底（330），具有给定光束发散的带电粒子束（320），并形成发散光束的带电粒子（360）通过使带电粒子束（320）经受能量场（350），从而使带电粒子束（320）具有较大的光束发散。该方法然后期望将发散的带电粒子束（360）植入衬底（330）中。

6. 发明申请

US20060073685A1 Method for implanting dopants within a substrate by tilting the substrate relative to the implant source 有权
标题翻译：通过使衬底相对于植入源倾斜来在衬底内注入掺杂剂的方法
公开(公告)号：US20060073685A1
公开(公告)日：2006-04-06
申请号：US10956583
申请日：2004-10-01
申请人： Said Ghneim , James Bernstein , Lance Robertson , Jiejie Xu , Jeffrey Loewecke
发明人： Said Ghneim , James Bernstein , Lance Robertson , Jiejie Xu , Jeffrey Loewecke
IPC分类号： H01J37/20 , H01L21/265 , H01L21/425
CPC分类号： H01L21/26586 , H01J2237/31701 , H01L21/823814 , Y10S438/914
摘要： The present invention provides a method for implanting a dopant in a substrate and a method for manufacturing a semiconductor device. The method for implanting a dopant, among other steps, including tilting a substrate (310) located on or over an implant platen (305) about an axis in a first direction with respect to an implant source (320) and implanting a portion of an implant dose within the substrate (310) tilted in the first direction. The method further includes tilting the substrate (310) having already been tilted in the first direction about the axis in a second opposite direction, and implanting at least a portion of the implant dose within the substrate (310) tilted in the second opposite direction.
摘要翻译：本发明提供了一种用于在衬底中注入掺杂剂的方法和用于制造半导体器件的方法。用于植入掺杂剂的方法以及其它步骤包括使位于植入物台板（305）上方或上方的衬底（310）相对于植入源（320）沿着第一方向的轴线倾斜并植入一部分在第一方向上倾斜的衬底（310）内的植入剂量。该方法还包括使已经在第一方向上沿第一方向倾斜的衬底（310）沿着第二相反方向围绕该轴线倾斜，并且将植入剂量的至少一部分植入衬底（310）内沿第二相反方向倾斜。

7. 发明申请

US20050245021A1 Semiconductor device having optimized shallow junction geometries and method for fabrication thereof 有权
标题翻译：具有优化的浅结几何形状的半导体器件及其制造方法
公开(公告)号：US20050245021A1
公开(公告)日：2005-11-03
申请号：US10835121
申请日：2004-04-29
申请人： Brian Hornung , Xin Zhang , Lance Robertson , Srinivasan Chakravarthi , P.R. Chidambaram
发明人： Brian Hornung , Xin Zhang , Lance Robertson , Srinivasan Chakravarthi , P.R. Chidambaram
IPC分类号： H01L21/8238
CPC分类号： H01L21/823814 , H01L21/823864
摘要： The present invention provides, in one embodiment, a method of fabricating a semiconductor device (100). The method comprises growing an oxide layer (120) on a gate structure (114) and a substrate (102) and implanting a dopant (124) into the substrate (102) and the oxide layer (120). Implantation is such that a portion of the dopant (124) remains in the oxide layer (120) to form an implanted oxide layer (126). The method further includes depositing a protective oxide layer (132) on the implanted oxide layer (126) and forming etch-resistant off-set spacers (134). The etch-resistant off-set spacers (134) are formed adjacent sidewalls of the gate structure (114) and on the protective oxide layer (132). The etch resistant off-set spacers having an inner perimeter (135) adjacent the sidewalls and an opposing outer perimeter (136). The method also comprises removing portions of the protective oxide layer (132) lying outside the outer perimeter (136) of the etch-resistant off-set spacers (134). Other embodiments of the present invention include a transistor device (200) and method of manufacturing an integrated circuit (300).
摘要翻译：本发明在一个实施例中提供一种制造半导体器件（100）的方法。该方法包括在栅极结构（114）和衬底（102）上生长氧化物层（120）并将掺杂剂（124）注入到衬底（102）和氧化物层（120）中。注入使得掺杂剂（124）的一部分保留在氧化物层（120）中以形成注入的氧化物层（126）。该方法还包括在注入的氧化物层（126）上沉积保护性氧化物层（132）并且形成耐腐蚀的偏置间隔物（134）。在栅极结构（114）的侧壁和保护氧化物层（132）上形成耐蚀刻偏置间隔物（134）。耐腐蚀的偏置间隔件具有邻近侧壁的内周边（135）和相对的外周边（136）。该方法还包括去除位于耐蚀刻偏移间隔物（134）的外周（136）外的保护氧化物层（132）的部分。本发明的其他实施例包括晶体管器件（200）和制造集成电路（300）的方法。

8. 发明申请

US20070257211A1 Implant Optimization Scheme 审中-公开
标题翻译：植入物优化方案
公开(公告)号：US20070257211A1
公开(公告)日：2007-11-08
申请号：US11772524
申请日：2007-07-02
申请人： James Bernstein , Lance Robertson , Said Ghneim , Nandu Mahalingam , Benjamin Moser
发明人： James Bernstein , Lance Robertson , Said Ghneim , Nandu Mahalingam , Benjamin Moser
IPC分类号： H01J37/08
CPC分类号： H01L21/26586 , H01L21/823814 , H01L29/66659
摘要： The present invention provides a method for implanting ions in a substrate and a method for manufacturing an integrated circuit. The method for implanting ions in a substrate, among other steps, including placing a substrate (410) on an implant platen (405) such that a predominant axes (430) of the substrate (410) is rotated about 30 degrees to about 60 degrees or about 120 degrees to about 150 degrees offset from a radial with respect to the implant platen (405), and further wherein the substrate (410) is not tilted. The method further includes implanting ions into the substrate (410), the rotated position of the predominant axes (430) reducing shadowing.
摘要翻译：本发明提供了一种在衬底中注入离子的方法和用于制造集成电路的方法。包括将衬底（410）放置在植入台板（405）上以使得衬底（410）的主轴（430）旋转约30度至约60度的方法或相对于植入台板（405）偏离径向的约120度至约150度，并且其中所述基底（410）不倾斜。该方法还包括将离子注入到基底（410）中，主轴（430）的旋转位置减少阴影。

9. 发明申请

US20050255683A1 Implant optimization scheme 有权
标题翻译：植入物优化方案
公开(公告)号：US20050255683A1
公开(公告)日：2005-11-17
申请号：US11006257
申请日：2004-12-07
申请人： James Bernstein , Lance Robertson , Said Ghneim , Nandu Mahalingam , Benjamin Moser
发明人： James Bernstein , Lance Robertson , Said Ghneim , Nandu Mahalingam , Benjamin Moser
IPC分类号： H01L21/265 , H01L21/336 , H01L21/425 , H01L21/76 , H01L21/8238
CPC分类号： H01L21/26586 , H01L21/823814 , H01L29/66659
摘要： The present invention provides a method for implanting ions in a substrate and a method for manufacturing an integrated circuit. The method for implanting ions in a substrate, among other steps, including placing a substrate (410) on an implant platen (405) such that a predominant axes (430) of the substrate (410) is rotated about 30 degrees to about 60 degrees or about 120 degrees to about 150 degrees offset from a radial with respect to the implant platen (405), and further wherein the substrate (410) is not tilted. The method further includes implanting ions into the substrate (410), the rotated position of the predominant axes (430) reducing shadowing.
摘要翻译：本发明提供了一种在衬底中注入离子的方法和用于制造集成电路的方法。包括将衬底（410）放置在植入台板（405）上以使得衬底（410）的主轴（430）旋转约30度至约60度的方法或相对于植入台板（405）偏离径向的约120度至约150度，并且其中所述基底（410）不倾斜。该方法还包括将离子注入到基底（410）中，主轴（430）的旋转位置减少阴影。

10. 发明申请

US20060001105A1 Semiconductor device having optimized shallow junction geometries and method for fabrication thereof 审中-公开
公开(公告)号：US20060001105A1
公开(公告)日：2006-01-05
申请号：US11179210
申请日：2005-07-12
申请人： Brian Hornung , Xin Zhang , Lance Robertson , Srinivasan Chakravarthi , P. Chidambaram
发明人： Brian Hornung , Xin Zhang , Lance Robertson , Srinivasan Chakravarthi , P. Chidambaram
IPC分类号： H01L29/76
CPC分类号： H01L21/823814 , H01L21/823864
摘要： The present invention provides, in one embodiment, a method of fabricating a semiconductor device (100). The method comprises growing an oxide layer (120) on a gate structure (114) and a substrate (102) and implanting a dopant (124) into the substrate (102) and the oxide layer (120). Implantation is such that a portion of the dopant (124) remains in the oxide layer (120) to form an implanted oxide layer (126). The method further includes depositing a protective oxide layer (132) on the implanted oxide layer (126) and forming etch-resistant off-set spacers (134). The etch-resistant off-set spacers (134) are formed adjacent sidewalls of the gate structure (114) and on the protective oxide layer (132). The etch resistant off-set spacers having an inner perimeter (135) adjacent the sidewalls and an opposing outer perimeter (136). The method also comprises removing portions of the protective oxide layer (132) lying outside the outer perimeter (136) of the etch-resistant off-set spacers (134). Other embodiments of the present invention include a transistor device (200) and method of manufacturing an integrated circuit (300).

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