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1. 发明授权

US08418008B2 Test technique to apply a variable scan clock including a scan clock modifier on an integrated circuit 有权
标题翻译：在集成电路上应用包括扫描时钟修改器的可变扫描时钟的测试技术
公开(公告)号：US08418008B2
公开(公告)日：2013-04-09
申请号：US12337629
申请日：2008-12-18
申请人： Sreejit Chakravarty , Narendra B. Devta-Prasa , Arun Gunda , Fan Yang
发明人： Sreejit Chakravarty , Narendra B. Devta-Prasa , Arun Gunda , Fan Yang
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G01R31/318552
摘要： A scan clock modifier, a method of providing a variable scan clock, an IC including a scan clock modifier and a library including a cell of a scan clock modifier. In one embodiment, the scan clock modifier includes: (1) logic circuitry configured to provide at least one selected clock signal based on a test scan clock signal and a first clock control signal, both of the test scan clock signal and the first clock control signal received from test equipment and (2) comparison logic configured to provide a scan clock signal based on the at least one selected clock signal and at least one other clock control signal received from the test equipment, wherein the first and the at least one other clock control signals are different clock control signals.
摘要翻译：扫描时钟修改器，提供可变扫描时钟的方法，包括扫描时钟修改器的IC和包括扫描时钟修改器的单元的库。在一个实施例中，扫描时钟修改器包括：（1）逻辑电路，被配置为基于测试扫描时钟信号和第一时钟控制信号提供至少一个选择的时钟信号，测试扫描时钟信号和第一时钟控制从所述测试设备接收的信号和（2）配置成基于所述至少一个所选择的时钟信号和从所述测试设备接收的至少一个其它时钟控制信号提供扫描时钟信号的比较逻辑，其中所述第一和所述至少一个其他时钟控制信号是不同的时钟控制信号。

2. 发明申请

US20100162060A1 DFT TECHNIQUE TO APPLY A VARIABLE SCAN CLOCK INCLUDING A SCAN CLOCK MODIFIER ON AN IC 有权
标题翻译： DFT技术在IC上应用可变扫描时钟，包括扫描时钟修改器
公开(公告)号：US20100162060A1
公开(公告)日：2010-06-24
申请号：US12337629
申请日：2008-12-18
申请人： Sreejit Chakravarty , Narendra B. Devta-Prasa , Arun Gunda , Fan Yang
发明人： Sreejit Chakravarty , Narendra B. Devta-Prasa , Arun Gunda , Fan Yang
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/318552
摘要： A scan clock modifier, a method of providing a variable scan clock, an IC including a scan clock modifier and a library including a cell of a scan clock modifier. In one embodiment, the scan clock modifier includes: (1) logic circuitry configured to provide at least one selected clock signal based on a test scan clock signal and a first clock control signal, both of the test scan clock signal and the first clock control signal received from test equipment and (2) comparison logic configured to provide a scan clock signal based on the at least one selected clock signal and at least one other clock control signal received from the test equipment, wherein the first and the at least one other clock control signals are different clock control signals.
摘要翻译：扫描时钟修改器，提供可变扫描时钟的方法，包括扫描时钟修改器的IC和包括扫描时钟修改器的单元的库。在一个实施例中，扫描时钟修改器包括：（1）逻辑电路，被配置为基于测试扫描时钟信号和第一时钟控制信号提供至少一个选择的时钟信号，测试扫描时钟信号和第一时钟控制从所述测试设备接收的信号和（2）配置成基于所述至少一个所选择的时钟信号和从所述测试设备接收的至少一个其它时钟控制信号提供扫描时钟信号的比较逻辑，其中所述第一和所述至少一个其他时钟控制信号是不同的时钟控制信号。

3. 发明申请

US20060242515A1 Systematic scan reconfiguration 失效
标题翻译：系统扫描重新配置
公开(公告)号：US20060242515A1
公开(公告)日：2006-10-26
申请号：US11114583
申请日：2005-04-26
申请人： Ahmad Alvamani , Narendra Devta-Prasanna , Arun Gunda
发明人： Ahmad Alvamani , Narendra Devta-Prasanna , Arun Gunda
IPC分类号： G01R31/28
CPC分类号： G01R31/318547
摘要： Methods for implementing test generation and test application for systematic scan reconfiguration in an integrated circuit. All detectable faults of the integrated circuit are added to a set F. A SAS decoder configuration is selected to start with. ATPG patterns are generated for the faults in the set F for the selected decoder configuration. When F=Ø, a set of patterns Pi is reported for each decoder configuration iεC, where C is a set of selected decoder configurations.
摘要翻译：用于实现集成电路中系统扫描重新配置的测试生成和测试应用的方法。集成电路的所有可检测故障都被添加到一个集合F.选择SAS解码器配置开始。为所选解码器配置的集合F中的故障生成ATPG模式。当F =Ø时，针对每个解码器配置iepsilonC报告一组模式P ，其中C是一组选择的解码器配置。

4. 发明授权

US07293210B2 System and method for improving transition delay fault coverage in delay fault tests through use of transition launch flip-flop 失效
标题翻译：通过使用转换启动触发器，在延迟故障测试中提高转换延迟故障覆盖的系统和方法
公开(公告)号：US07293210B2
公开(公告)日：2007-11-06
申请号：US11124438
申请日：2005-05-06
申请人： Arun Gunda , Narendra Devta-Prasanna
发明人： Arun Gunda , Narendra Devta-Prasanna
IPC分类号： G01R31/28
CPC分类号： G01R31/318541 , G01R31/31858
摘要： The present invention is directed to a system and method for improving transition delay fault coverage through use of augmented flip-flops (TL flops) for a broadside test approach. The TL flops use the same clock for scan and functional operation. Thus, the TL flops do not require a fast signal switching between launch and test response capture. Each of the TL flops includes additional multiplexer in front of a standard scan flop and a transition enable (TEN) signal. Moreover, only a heuristically selected subset of scan flip-flops is replaced with the TL flops and only one additional MUX per selected scan flip-flop may contribute an area overhead. Consequently, the overall chip area overhead may be minimal. The present invention may be suitable for being implemented with currently available third party ATPG.
摘要翻译：本发明涉及一种用于通过使用扩展触发器（TL触发器）来进行宽边测试方法来改善转换延迟故障覆盖的系统和方法。 TL触发器使用相同的时钟进行扫描和功能操作。因此，TL触发器不需要在发射和测试响应捕获之间的快速信号切换。每个TL触发器在标准扫描触发器之前包括附加多路复用器和转换使能（TEN）信号。此外，只有一个启发式选择的扫描触发器子集被TL触发器替代，并且每个所选择的扫描触发器只有一个额外的MUX可以贡献一个区域开销。因此，整个芯片面积开销可能是最小的。本发明可适用于使用当前可用的第三方ATPG来实现。

5. 发明授权

US5903578A Test shells for protecting proprietary information in asic cores 失效
标题翻译：测试shell用于保护asic内核中的专有信息
公开(公告)号：US5903578A
公开(公告)日：1999-05-11
申请号：US611325
申请日：1996-03-08
申请人： Kaushik De , Siva Venkatraman , Arun Gunda
发明人： Kaushik De , Siva Venkatraman , Arun Gunda
IPC分类号： G01R31/3185 , G01R31/28
CPC分类号： G01R31/318558
摘要： A reduced netlist representing only partial netlist information for a logic block such as an ASIC embedded core is generated, such that proprietary information contained within the netlist can be kept confidential. The core is conceptually divided into a first section that can be completely tested using only a serial scan port, and a second section that can be tested in isolation from the first section using both primary inputs to the core as well as scan inputs. Netlist information for the first section is removed from the netlist, and the customer is supplied with serial scan test vectors that test the first section. Additionally, a multiplexing circuit selects either a serial scan chain for the entire logic block, or a scan chain that does not include scan cells within the first section of the logic bloc.
摘要翻译：生成仅代表诸如ASIC嵌入式核心的逻辑块的部分网表信息的减少的网表，使得包含在网表内的专有信息可以被保密。核心在概念上分为第一部分，可以使用只有串行扫描端口进行完全测试，第二部分可以使用主输入到核心以及扫描输入的第一部分进行隔离测试。第一节的网表信息从网表中删除，客户提供测试第一部分的串行扫描测试向量。此外，复用电路选择整个逻辑块的串行扫描链，或者不包括在逻辑块的第一部分内的扫描单元的扫描链。

6. 发明授权

US07461307B2 System and method for improving transition delay fault coverage in delay fault tests through use of an enhanced scan flip-flop 失效
标题翻译：通过使用增强型扫描触发器来延迟故障测试中的转换延迟故障覆盖的系统和方法
公开(公告)号：US07461307B2
公开(公告)日：2008-12-02
申请号：US11123432
申请日：2005-05-06
申请人： Arun Gunda , Narendra Devta-Prasanna
发明人： Arun Gunda , Narendra Devta-Prasanna
IPC分类号： G01R31/28
CPC分类号： G01R31/31858 , G01R31/318541
摘要： The present invention is directed to a system and method for improving transition delay test coverage through use of enhanced flip flops (ES flip-flops) for a broadside test approach. Each ES flip-flop includes a two port flip-flop including a first flip-flop and a second flip-flop. A separate control input (ESM) which is not time critical is used to select a multiplexer of the second flip-flop. Thus, the ES flip-flops do not require a fast signal switching between launch and test response capture or an extra clock signal. Various enhanced scan modes may be selected via a combination of SEN and ESM. Moreover, only a heuristically selected subset of scan flip-flops may be replaced with the ES flip-flops so as to minimize the length of a scan chain as well as the logic area overhead. The present invention provides high TDF coverage under the broadside testing.
摘要翻译：本发明涉及一种用于通过使用增强型触发器（ES触发器）用于宽边测试方法来改进转换延迟测试覆盖的系统和方法。每个ES触发器包括包括第一触发器和第二触发器的双端口触发器。使用不是时间关键的单独的控制输入（ESM）来选择第二个触发器的多路复用器。因此，ES触发器不需要在发射和测试响应捕获之间的快速信号切换或额外的时钟信号。可以通过SEN和ESM的组合来选择各种增强的扫描模式。此外，只有启发式选择的扫描触发器子集可以被ES触发器替代，以便使扫描链的长度以及逻辑区开销最小化。本发明在宽边测试下提供高TDF覆盖。

7. 发明申请

US20060253754A1 System and method for improving transition delay fault coverage in delay fault tests through use of transition launch flip-flop 失效
标题翻译：通过使用转换启动触发器，在延迟故障测试中提高转换延迟故障覆盖的系统和方法
公开(公告)号：US20060253754A1
公开(公告)日：2006-11-09
申请号：US11124438
申请日：2005-05-06
申请人： Arun Gunda , Narendra Devta-Prasanna
发明人： Arun Gunda , Narendra Devta-Prasanna
IPC分类号： G01R31/28
CPC分类号： G01R31/318541 , G01R31/31858
摘要： The present invention is directed to a system and method for improving transition delay fault coverage through use of augmented flip-flops (TL flops) for a broadside test approach. The TL flops use the same clock for scan and functional operation. Thus, the TL flops do not require a fast signal switching between launch and test response capture. Each of the TL flops includes additional multiplexer in front of a standard scan flop and a transition enable (TEN) signal. Moreover, only a heuristically selected subset of scan flip-flops is replaced with the TL flops and only one additional MUX per selected scan flip-flop may contribute an area overhead. Consequently, the overall chip area overhead may be minimal. The present invention may be suitable for being implemented with currently available third party ATPG.
摘要翻译：本发明涉及一种用于通过使用扩展触发器（TL触发器）来进行宽边测试方法来改善转换延迟故障覆盖的系统和方法。 TL触发器使用相同的时钟进行扫描和功能操作。因此，TL触发器不需要在发射和测试响应捕获之间的快速信号切换。每个TL触发器在标准扫描触发器之前包括附加多路复用器和转换使能（TEN）信号。此外，只有一个启发式选择的扫描触发器子集被TL触发器替代，并且每个所选择的扫描触发器只有一个额外的MUX可以贡献一个区域开销。因此，整个芯片面积开销可能是最小的。本发明可适用于使用当前可用的第三方ATPG来实现。

8. 发明授权

US07555688B2 Method for implementing test generation for systematic scan reconfiguration in an integrated circuit 失效
标题翻译：用于实现集成电路中系统扫描重新配置的测试生成的方法
公开(公告)号：US07555688B2
公开(公告)日：2009-06-30
申请号：US11114583
申请日：2005-04-26
申请人： Ahmad A. Alvamani , Narendra Devta-Prasanna , Arun Gunda
发明人： Ahmad A. Alvamani , Narendra Devta-Prasanna , Arun Gunda
IPC分类号： G01R31/28
CPC分类号： G01R31/318547
摘要： A method for implementing test generation for systematic scan reconfiguration in an integrated circuit is presented. The method may comprise: defining at least one set of detectable faults; setting an SAS decoder configuration, the SAS decoder configuration including a don't-care bit; generating an ATPG pattern; and applying the ATPG pattern to one or more scan chain segments having a segment address associated with the SAS decoder configuration.
摘要翻译：提出了一种用于实现集成电路中系统扫描重配置的测试生成的方法。该方法可以包括：定义至少一组可检测的故障; 设置SAS解码器配置，SAS解码器配置包括不需要的位; 产生ATPG模式; 以及将ATPG模式应用于具有与SAS解码器配置相关联的段地址的一个或多个扫描链段。

9. 发明授权

US07461315B2 Method and system for improving quality of a circuit through non-functional test pattern identification 失效
标题翻译：通过非功能测试模式识别提高电路质量的方法和系统
公开(公告)号：US07461315B2
公开(公告)日：2008-12-02
申请号：US11124649
申请日：2005-05-09
申请人： Arun Gunda , Narendra Devta-Prasanna
发明人： Arun Gunda , Narendra Devta-Prasanna
IPC分类号： G01R31/28
CPC分类号： G01R31/318328 , G01R31/31835
摘要： The present invention is directed to a system and method for quality improvement by identifying test patterns for DFT logic faults and functional logic faults. The identified test patterns may be selectively utilized for pruning of patterns or DPM estimation. Functional faults and DFT faults may be identified from detected TDF faults. The functional faults are faults on a logic which was present in a pre-test insertion net list. Remaining faults are the DFT faults. A set of test patterns for DFT faults may be utilized as the first target for the pattern truncation which will reduce the amount of test patterns to be tested. A set of test patterns for functional may be utilized for improving the TDF coverage.
摘要翻译：本发明涉及一种用于通过识别DFT逻辑故障和功能逻辑故障的测试模式来提高质量的系统和方法。可以选择性地使用所识别的测试图案来修剪图案或DPM估计。功能故障和DFT故障可以从检测到的TDF故障中识别。功能故障是存在于测试前插入网络列表中的逻辑故障。剩余故障是DFT故障。用于DFT故障的一组测试模式可以用作模式截断的第一个目标，这将减少要测试的测试模式的数量。可以使用一组用于功能的测试模式来改善TDF覆盖。

10. 发明申请

US20060136795A1 Method of testing scan chain integrity and tester setup for scan block testing 审中-公开
标题翻译：扫描链完整性测试方法和扫描块测试的测试仪设置
公开(公告)号：US20060136795A1
公开(公告)日：2006-06-22
申请号：US11016412
申请日：2004-12-17
申请人： Arun Gunda , Thai Nguyen
发明人： Arun Gunda , Thai Nguyen
IPC分类号： G01R31/28
CPC分类号： G01R31/318544
摘要： A method of scan chain integrity testing for an integrated circuit design includes steps of: (a) receiving as input an integrated circuit design; (b) generating a partial shift test bench for the integrated circuit design wherein the partial shift test bench includes scan chains stitched together into shift registers and a scan block; (c) parallel loading the scan chains with a set of test vectors from the scan block with an offset of N bits wherein N is a number greater than one and less than the maximum length of the scan chains; (d) shifting the last N bits of the test vectors into the scan chains with N scan clock pulses; (e) comparing outputs of the scan chains with expected values in the scan block to produce a scan chain integrity test result; and (f) generating as output the scan chain integrity test result.
摘要翻译：一种用于集成电路设计的扫描链完整性测试的方法包括以下步骤：（a）作为输入接收集成电路设计; （b）产生用于集成电路设计的部分移位测试台，其中部分移位测试台包括缝合在一起的移位寄存器和扫描块的扫描链; （c）使用来自具有N位偏移的扫描块的一组测试向量并行加载扫描链，其中N是大于1且小于扫描链的最大长度的数字; （d）用N个扫描时钟脉冲将测试矢量的最后N位移动到扫描链中; （e）将扫描链的输出与扫描块中的期望值进行比较以产生扫描链完整性测试结果; 和（f）产生扫描链完整性测试结果作为输出。

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