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1. 发明申请

US20110090920A1 PACKET COALESCING 有权
标题翻译：包装包装
公开(公告)号：US20110090920A1
公开(公告)日：2011-04-21
申请号：US12980682
申请日：2010-12-29
申请人： Srihari Makineni , Ravi Iyer , Dave Minturn , Sujoy Sen , Donald Newell , Li Zhao
发明人： Srihari Makineni , Ravi Iyer , Dave Minturn , Sujoy Sen , Donald Newell , Li Zhao
IPC分类号： H04L12/66
CPC分类号： H04L45/74 , H04L49/20 , H04L69/16 , H04L69/161 , H04L69/166
摘要： In general, in one aspect, the disclosures describes a method that includes receiving multiple ingress Internet Protocol packets, each of the multiple ingress Internet Protocol packets having an Internet Protocol header and a Transmission Control Protocol segment having a Transmission Control Protocol header and a Transmission Control Protocol payload, where the multiple packets belonging to a same Transmission Control Protocol/Internet Protocol flow. The method also includes preparing an Internet Protocol packet having a single Internet Protocol header and a single Transmission Control Protocol segment having a single Transmission Control Protocol header and a single payload formed by a combination of the Transmission Control Protocol segment payloads of the multiple Internet Protocol packets. The method further includes generating a signal that causes receive processing of the Internet Protocol packet.
摘要翻译：一般来说，一方面，本公开内容描述了一种方法，其包括接收多个入口因特网协议分组，所述多个入口因特网协议分组中的每一个具有因特网协议报头和具有传输控制协议报头和传输控制的传输控制协议段协议有效载荷，其中属于相同传输控制协议/因特网协议的多个分组流。该方法还包括准备具有单个因特网协议报头的互联网协议分组和具有单个传输控制协议报头的单个传输控制协议段和由多个因特网协议分组的传输控制协议段有效载荷的组合形成的单个有效载荷。该方法还包括产生导致因特网协议分组的接收处理的信号。

2. 发明授权

US08036246B2 Packet coalescing 有权
标题翻译：分组聚合
公开(公告)号：US08036246B2
公开(公告)日：2011-10-11
申请号：US12586964
申请日：2009-09-30
申请人： Srihari Makineni , Ravi Iyer , Dave Minturn , Sujoy Sen , Donald Newell , Li Zhao
发明人： Srihari Makineni , Ravi Iyer , Dave Minturn , Sujoy Sen , Donald Newell , Li Zhao
IPC分类号： H04J3/24
CPC分类号： H04L45/74 , H04L49/20 , H04L69/16 , H04L69/161 , H04L69/166
摘要： In general, in one aspect, the disclosures describes a method that includes receiving multiple ingress Internet Protocol packets, each of the multiple ingress Internet Protocol packets having an Internet Protocol header and a Transmission Control Protocol segment having a Transmission Control Protocol header and a Transmission Control Protocol payload, where the multiple packets belonging to a same Transmission Control Protocol/Internet Protocol flow. The method also includes preparing an Internet Protocol packet having a single Internet Protocol header and a single Transmission Control Protocol segment having a single Transmission Control Protocol header and a single payload formed by a combination of the Transmission Control Protocol segment payloads of the multiple Internet Protocol packets. The method further includes generating a signal that causes receive processing of the Internet Protocol packet.
摘要翻译：一般来说，一方面，本公开内容描述了一种方法，其包括接收多个入口因特网协议分组，所述多个入口因特网协议分组中的每一个具有因特网协议报头和具有传输控制协议报头和传输控制的传输控制协议段协议有效载荷，其中属于相同传输控制协议/因特网协议的多个分组流。该方法还包括准备具有单个因特网协议报头的互联网协议分组和具有单个传输控制协议报头的单个传输控制协议段和由多个因特网协议分组的传输控制协议段有效载荷的组合形成的单个有效载荷。该方法还包括产生导致因特网协议分组的接收处理的信号。

3. 发明申请

US20100020819A1 Packet coalescing 有权
标题翻译：分组聚合
公开(公告)号：US20100020819A1
公开(公告)日：2010-01-28
申请号：US12586964
申请日：2009-09-30
申请人： Srihari Makineni , Ravi Iyer , Dave Minturn , Sujoy Sen , Donald Newell , Li Zhao
发明人： Srihari Makineni , Ravi Iyer , Dave Minturn , Sujoy Sen , Donald Newell , Li Zhao
IPC分类号： H04L12/66
CPC分类号： H04L45/74 , H04L49/20 , H04L69/16 , H04L69/161 , H04L69/166
摘要： In general, in one aspect, the disclosures describes a method that includes receiving multiple ingress Internet Protocol packets, each of the multiple ingress Internet Protocol packets having an Internet Protocol header and a Transmission Control Protocol segment having a Transmission Control Protocol header and a Transmission Control Protocol payload, where the multiple packets belonging to a same Transmission Control Protocol/Internet Protocol flow. The method also includes preparing an Internet Protocol packet having a single Internet Protocol header and a single Transmission Control Protocol segment having a single Transmission Control Protocol header and a single payload formed by a combination of the Transmission Control Protocol segment payloads of the multiple Internet Protocol packets. The method further includes generating a signal that causes receive processing of the Internet Protocol packet.
摘要翻译：一般来说，一方面，本公开内容描述了一种方法，其包括接收多个入口因特网协议分组，所述多个入口因特网协议分组中的每一个具有因特网协议报头和具有传输控制协议报头和传输控制的传输控制协议段协议有效载荷，其中属于相同传输控制协议/因特网协议的多个分组流。该方法还包括准备具有单个因特网协议报头的互联网协议分组和具有单个传输控制协议报头的单个传输控制协议段和由多个因特网协议分组的传输控制协议段有效载荷的组合形成的单个有效载荷。该方法还包括产生导致因特网协议分组的接收处理的信号。

4. 发明授权

US07620071B2 Packet coalescing 有权
标题翻译：分组聚合
公开(公告)号：US07620071B2
公开(公告)日：2009-11-17
申请号：US10991239
申请日：2004-11-16
申请人： Srihari Makineni , Ravi Iyer , Dave Minturn , Sujoy Sen , Donald Newell , Li Zhao
发明人： Srihari Makineni , Ravi Iyer , Dave Minturn , Sujoy Sen , Donald Newell , Li Zhao
IPC分类号： H04J3/24
CPC分类号： H04L45/74 , H04L49/20 , H04L69/16 , H04L69/161 , H04L69/166
摘要： In general, in one aspect, the disclosures describes a method that includes receiving multiple ingress Internet Protocol packets, each of the multiple ingress Internet Protocol packets having an Internet Protocol header and a Transmission Control Protocol segment having a Transmission Control Protocol header and a Transmission Control Protocol payload, where the multiple packets belonging to a same Transmission Control Protocol/Internet Protocol flow. The method also includes preparing an Internet Protocol packet having a single Internet Protocol header and a single Transmission Control Protocol segment having a single Transmission Control Protocol header and a single payload formed by a combination of the Transmission Control Protocol segment payloads of the multiple Internet Protocol packets. The method further includes generating a signal that causes receive processing of the Internet Protocol packet.
摘要翻译：一般来说，一方面，本公开内容描述了一种方法，其包括接收多个入口因特网协议分组，所述多个入口因特网协议分组中的每一个具有因特网协议报头和具有传输控制协议报头和传输控制的传输控制协议段协议有效载荷，其中属于相同传输控制协议/因特网协议的多个分组流。该方法还包括准备具有单个因特网协议报头的互联网协议分组和具有单个传输控制协议报头的单个传输控制协议段和由多个因特网协议分组的传输控制协议段有效载荷的组合形成的单个有效载荷。该方法还包括产生导致因特网协议分组的接收处理的信号。

5. 发明申请

US20060104303A1 Packet coalescing 有权
公开(公告)号：US20060104303A1
公开(公告)日：2006-05-18
申请号：US10991239
申请日：2004-11-16
申请人： Srihari Makineni , Ravi Iyer , Dave Minturn , Sujoy Sen , Donald Newell , Li Zhao
发明人： Srihari Makineni , Ravi Iyer , Dave Minturn , Sujoy Sen , Donald Newell , Li Zhao
IPC分类号： H04L12/28
CPC分类号： H04L45/74 , H04L49/20 , H04L69/16 , H04L69/161 , H04L69/166
摘要： In general, in one aspect, the disclosures describes a method that includes receiving multiple ingress Internet Protocol packets, each of the multiple ingress Internet Protocol packets having an Internet Protocol header and a Transmission Control Protocol segment having a Transmission Control Protocol header and a Transmission Control Protocol payload, where the multiple packets belonging to a same Transmission Control Protocol/Internet Protocol flow. The method also includes preparing an Internet Protocol packet having a single Internet Protocol header and a single Transmission Control Protocol segment having a single Transmission Control Protocol header and a single payload formed by a combination of the Transmission Control Protocol segment payloads of the multiple Internet Protocol packets. The method further includes generating a signal that causes receive processing of the Internet Protocol packet.

6. 发明申请

US20140211804A1 PACKET COALESCING 有权
标题翻译：包装包装
公开(公告)号：US20140211804A1
公开(公告)日：2014-07-31
申请号：US14229545
申请日：2014-03-28
申请人： Srihari Makikeni , Ravi lyer , Dave Minturn , Sujoy Sen , Donald Newell , Li Zhao
发明人： Srihari Makikeni , Ravi lyer , Dave Minturn , Sujoy Sen , Donald Newell , Li Zhao
IPC分类号： H04L12/741 , H04L12/931
CPC分类号： H04L45/74 , H04L49/20 , H04L69/16 , H04L69/161 , H04L69/166
摘要： In general, in one aspect, the disclosures describes a method that includes receiving multiple ingress Internet Protocol packets, each of the multiple ingress Internet Protocol packets having an Internet Protocol header and a Transmission Control Protocol segment having a Transmission Control Protocol header and a Transmission Control Protocol payload, where the multiple packets belonging to a same Transmission Control Protocol/Internet Protocol flow. The method also includes preparing an Internet Protocol packet having a single Internet Protocol header and a single Transmission Control Protocol segment having a single Transmission Control Protocol header and a single payload formed by a combination of the Transmission Control Protocol segment payloads of the multiple Internet Protocol packets. The method further includes generating a signal that causes receive processing of the Internet Protocol packet.
摘要翻译：一般来说，一方面，本公开内容描述了一种方法，其包括接收多个入口因特网协议分组，所述多个入口因特网协议分组中的每一个具有因特网协议报头和具有传输控制协议报头和传输控制的传输控制协议段协议有效载荷，其中属于相同传输控制协议/因特网协议的多个分组流。该方法还包括准备具有单个因特网协议报头的互联网协议分组和具有单个传输控制协议报头的单个传输控制协议段和由多个因特网协议分组的传输控制协议段有效载荷的组合形成的单个有效载荷。该方法还包括产生导致因特网协议分组的接收处理的信号。

7. 发明授权

US07581042B2 I/O hub resident cache line monitor and device register update 有权
标题翻译： I / O集线器驻留高速缓存行监视器和设备寄存器更新
公开(公告)号：US07581042B2
公开(公告)日：2009-08-25
申请号：US11026928
申请日：2004-12-29
申请人： Dave Minturn , James B. Crossland , Sujoy Sen , Greg Cummings
发明人： Dave Minturn , James B. Crossland , Sujoy Sen , Greg Cummings
IPC分类号： G06F3/00
CPC分类号： G06F12/0875 , G06F12/0862
摘要： The apparatus and method described herein are for enabling cacheable writes to I/O device registers. A cache monitor, which may be present in a controller hub, monitors accesses to cache lines in a microprocessor. The cache monitor also associates cache lines in the microprocessor with I/O device registers. When an access to certain cache lines are detected, the cache monitor is operable to receive the contents of the cache line and write those contents to an associated I/O device register. Therefore, a microprocessor may write to a cache line, instead of making an uncacheable write to the I/O device register directly.
摘要翻译：本文描述的装置和方法用于实现对I / O设备寄存器的可高速缓存写入。可能存在于控制器集线器中的高速缓存监视器监视对微处理器中的高速缓存行的访问。高速缓存监视器还将微处理器中的高速缓存行与I / O设备寄存器相关联。当检测到对某些高速缓存行的访问时，高速缓存监视器可操作以接收高速缓存行的内容并将这些内容写入相关联的I / O设备寄存器。因此，微处理器可以写入高速缓存线，而不是直接对I / O设备寄存器进行不可写的写操作。

8. 发明申请

US20060143333A1 I/O hub resident cache line monitor and device register update 有权
公开(公告)号：US20060143333A1
公开(公告)日：2006-06-29
申请号：US11026928
申请日：2004-12-29
申请人： Dave Minturn , James Crossland , Sujoy Sen , Greg Cummings
发明人： Dave Minturn , James Crossland , Sujoy Sen , Greg Cummings
IPC分类号： G06F5/00 , G06F12/00
CPC分类号： G06F12/0875 , G06F12/0862
摘要： The apparatus and method described herein are for enabling cacheable writes to I/O device registers. A cache monitor, which may be present in a controller hub, monitors accesses to cache lines in a microprocessor. The cache monitor also associates cache lines in the microprocessor with I/O device registers. When an access to certain cache lines are detected, the cache monitor is operable to receive the contents of the cache line and write those contents to an associated I/O device register. Therefore, a microprocessor may write to a cache line, instead of making an uncacheable write to the I/O device register directly.

9. 发明申请

US20050144422A1 Virtual to physical address translation 审中-公开
标题翻译：虚拟到物理地址转换
公开(公告)号：US20050144422A1
公开(公告)日：2005-06-30
申请号：US10750567
申请日：2003-12-30
申请人： Gary McAlpine , Dave Minturn , Greg Regnier , Frank Berry
发明人： Gary McAlpine , Dave Minturn , Greg Regnier , Frank Berry
IPC分类号： G06F12/02 , G06F12/10 , G06F12/14 , G06F12/08
CPC分类号： G06F12/1081 , G06F12/1036 , G06F12/109 , G06F12/1458
摘要： A virtual to physical address translator in which a requesting process supplements a virtual memory address with a shortcut to a physical address associated with one level of a multi-level virtual address translation table. A second process, such as an I/O process, receives the shortcut and the virtual address and uses an address translator to determine the physical address. In some implementations, the shortcut may be made opaque to the requesting process such that the requesting process cannot determine the physical address represented in the shortcut.
摘要翻译：一种虚拟到物理地址转换器，其中请求过程利用与多级虚拟地址转换表的一个级别相关联的物理地址的快捷方式来补充虚拟存储器地址。诸如I / O进程的第二进程接收快捷方式和虚拟地址，并使用地址转换器来确定物理地址。在一些实施方案中，快捷方式可以对请求过程变得不透明，使得请求进程不能确定快捷方式中表示的物理地址。

10. 发明申请

US20050058147A1 Method for providing prioritized data movement between endpoints connected by multiple logical channels 有权
标题翻译：用于在通过多个逻辑信道连接的端点之间提供优先数据移动的方法
公开(公告)号：US20050058147A1
公开(公告)日：2005-03-17
申请号：US10973306
申请日：2004-10-27
申请人： Greg Regnier , Jeffrey Butler , Dave Minturn
发明人： Greg Regnier , Jeffrey Butler , Dave Minturn
IPC分类号： H04L12/56
CPC分类号： H04L47/18 , H04L47/10 , H04L47/16 , H04L47/2441 , H04L47/245 , H04L49/101 , H04L49/1515 , H04L49/205 , H04L49/3072
摘要： A data network and a method for providing prioritized data movement between endpoints connected by multiple logical channels. Such a data network may include a first node comprising a first plurality of first-in, first-out (FIFO) queues arranged for high priority to low priority data movement operations; and a second node operatively connected to the first node by multiple control and data channels, and comprising a second plurality of FIFO queues arranged in correspondence with the first plurality of FIFO queues for high priority to low priority data movement operations via the multiple control and data channels; wherein an I/O transaction is accomplished by one or more control channels and data channels created between the first node and the second node for moving commands and data for the I/O transaction during the data movement operations, in the order from high priority to low priority.
摘要翻译：数据网络和用于在由多个逻辑信道连接的端点之间提供优先数据移动的方法。这样的数据网络可以包括第一节点，其包括被布置为高优先级到低优先级数据移动操作的第一多个先入先出（FIFO）队列; 以及第二节点，其通过多个控制和数据信道可操作地连接到所述第一节点，并且包括经由所述多个控制和数据的高优先级到低优先级数据移动操作而对应于所述第一多个FIFO队列排列的第二多个FIFO队列渠道; 其中通过在第一节点和第二节点之间创建的一个或多个控制信道和数据信道来实现I / O事务，用于在数据移动操作期间以从高优先级到高级优先级到高级优先级的顺序移动用于I / O事务的命令和数据低优先级。

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