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1. 发明申请

US20180175832A1 POWER SWITCHING CIRCUITRY INCLUDING POWER-UP CONTROL 审中-公开
公开(公告)号：US20180175832A1
公开(公告)日：2018-06-21
申请号：US15382076
申请日：2016-12-16
申请人： Suphachai Chai Sutanthavibul , Iqbal Rajwani , Anupama A. Thaploo , Surya Sasi Tallapragada , Daivik H. Bhatt , Lei Jiang , Stephen Kim , Pascal A. Meinerzhagen , Muhammad M. Khellah
发明人： Suphachai Chai Sutanthavibul , Iqbal Rajwani , Anupama A. Thaploo , Surya Sasi Tallapragada , Daivik H. Bhatt , Lei Jiang , Stephen Kim , Pascal A. Meinerzhagen , Muhammad M. Khellah
IPC分类号： H03K3/012 , H02M1/08
CPC分类号： H02M1/08 , H02M1/088 , H02M3/158 , H02M2001/0032 , H02M2001/0048 , H03K17/08122 , H03K17/6871 , H03K19/0013 , H03K19/0016 , H03K2017/0806 , H03K2217/0036 , Y02B70/1491
摘要： Some embodiments include apparatuses and methods using the apparatuses. One of the apparatuses includes a first power supply node, a second power supply node, transistors coupled in parallel between the first and second power supply nodes, and a controller to provide a first voltage, a second voltage, and a third voltage to gates of the transistors based on digital information. The first, second, and third voltages have different values based on values of the digital information.

2. 发明授权

US07130236B2 Low power delay controlled zero sensitive sense amplifier 有权
标题翻译：低功耗延迟控制零敏感读出放大器
公开(公告)号：US07130236B2
公开(公告)日：2006-10-31
申请号：US11081276
申请日：2005-03-16
申请人： Iqbal Rajwani , Satish Damaraju
发明人： Iqbal Rajwani , Satish Damaraju
IPC分类号： G11C7/02
CPC分类号： G11C7/12 , G11C7/062 , G11C7/067
摘要： In one embodiment of the invention an integrated circuit is provided including a sense amplifier to read data from a memory cell that has a first transfer gate, a second transfer gate, a comparator, and a control circuit. The first transfer gate has a first pole coupled to a positive power supply. The second transfer gate has a first pole coupled to a bitline of the memory cell. The comparator has a first input coupled to a second pole of the first transfer gate, a second input coupled to a second pole of the second transfer gate, and an output coupled to the second input. The comparator compares signals on the first and second inputs and selectively generates a greater differential signal there-between. The control circuit turns off the comparator responsive to a logical zero being read from the memory cell avoiding the generation of the greater differential signal.
摘要翻译：在本发明的一个实施例中，提供一种集成电路，其包括用于从具有第一传输门，第二传输门，比较器和控制电路的存储单元读取数据的读出放大器。第一传输门具有耦合到正电源的第一极。第二传输门具有耦合到存储单元的位线的第一极。比较器具有耦合到第一传输门的第二极的第一输入，耦合到第二传输门的第二极的第二输入和耦合到第二输入的输出。比较器比较第一和第二输入端的信号，并选择性地在其间产生较大的差分信号。控制电路响应于从存储器单元读取的逻辑零而关闭比较器，从而避免产生更大的差分信号。

3. 发明申请

US20150279438A1 ASSIST CIRCUIT FOR MEMORY 有权
标题翻译：记忆辅助电路
公开(公告)号：US20150279438A1
公开(公告)日：2015-10-01
申请号：US14229767
申请日：2014-03-28
申请人： Jaydeep P. Kulkarni , Anupama Thaploo , Iqbal Rajwani , Kyung-Hoae Koo , Eric A. Karl , Muhammad Khellah
发明人： Jaydeep P. Kulkarni , Anupama Thaploo , Iqbal Rajwani , Kyung-Hoae Koo , Eric A. Karl , Muhammad Khellah
IPC分类号： G11C7/12 , G11C17/16 , G11C7/22
CPC分类号： G11C7/12 , G11C7/1048 , G11C7/1069 , G11C7/22 , G11C11/419 , G11C17/16 , G11C2207/005
摘要： Embodiments include apparatuses, methods, and systems related to an assist circuit that may be coupled to one or more components of a memory system to selectively lower a supply voltage that is delivered to the component. For example, the assist circuit may be coupled to a plurality of bitcells (e.g., register file bitcells). The assist circuit may selectively lower the supply voltage delivered to the bitcells during at least a portion of a write operation and/or during an inactive state of the bitcells. Additionally, or alternatively, the assist circuit may be coupled to a read circuit to selectively lower the supply voltage delivered to the read circuit during an inactive state of the read circuit. The assist circuit may include a control transistor coupled in parallel with one or more diodes between a main supply rail and a supply node of the bitcells and/or read circuit.
摘要翻译：实施例包括与可以耦合到存储器系统的一个或多个部件的辅助电路相关的装置，方法和系统，以选择性地降低传送到部件的电源电压。例如，辅助电路可以耦合到多个比特单元（例如，寄存器文件比特单元）。辅助电路可以在写入操作的至少一部分期间和/或在位单元的非活动状态期间选择性地降低传送到位单元的电源电压。另外或替代地，辅助电路可以耦合到读取电路，以在读取电路的非活动状态期间选择性地降低传送到读取电路的电源电压。辅助电路可以包括与主电源轨和位单元和/或读电路的供电节点之间的一个或多个二极管并联耦合的控制晶体管。

4. 发明申请

US20060209606A1 LOW POWER DELAY CONTROLLED ZERO SENSITIVE SENSE AMPLIFIER 有权
标题翻译：低功率延迟控制的零感应感测放大器
公开(公告)号：US20060209606A1
公开(公告)日：2006-09-21
申请号：US11081276
申请日：2005-03-16
申请人： Iqbal Rajwani , Satish Damaraju
发明人： Iqbal Rajwani , Satish Damaraju
IPC分类号： G11C7/00
CPC分类号： G11C7/12 , G11C7/062 , G11C7/067
摘要： In one embodiment of the invention an integrated circuit is provided including a sense amplifier to read data from a memory cell that has a first transfer gate, a second transfer gate, a comparator, and a control circuit. The first transfer gate has a first pole coupled to a positive power supply. The second transfer gate has a first pole coupled to a bitline of the memory cell. The comparator has a first input coupled to a second pole of the first transfer gate, a second input coupled to a second pole of the second transfer gate, and an output coupled to the second input. The comparator compares signals on the first and second inputs and selectively generates a greater differential signal there-between. The control circuit turns off the comparator responsive to a logical zero being read from the memory cell avoiding the generation of the greater differential signal.
摘要翻译：在本发明的一个实施例中，提供一种集成电路，其包括用于从具有第一传输门，第二传输门，比较器和控制电路的存储单元读取数据的读出放大器。第一传输门具有耦合到正电源的第一极。第二传输门具有耦合到存储单元的位线的第一极。比较器具有耦合到第一传输门的第二极的第一输入，耦合到第二传输门的第二极的第二输入和耦合到第二输入的输出。比较器比较第一和第二输入端的信号，并选择性地在其间产生较大的差分信号。控制电路响应于从存储器单元读取的逻辑零而关闭比较器，从而避免产生更大的差分信号。

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