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1. 发明申请

US20080213995A1 Ultrasonic electropolishing of conductive material 审中-公开
标题翻译：超声波电解抛光导电材料
公开(公告)号：US20080213995A1
公开(公告)日：2008-09-04
申请号：US11713215
申请日：2007-03-02
申请人： Tatyana N. Andryushchenko , Radek P. Chalupa , Anne E. Miller , Lei Jiang
发明人： Tatyana N. Andryushchenko , Radek P. Chalupa , Anne E. Miller , Lei Jiang
IPC分类号： H01L21/44 , C25D17/00
CPC分类号： C25D5/02 , C25D7/123 , C25F3/30 , H01L21/32115 , H01L21/7684
摘要： In one embodiment, the present invention includes a method for forming a dielectric layer on a semiconductor wafer and patterning at least one opening in the dielectric layer, depositing a barrier layer over the dielectric layer, depositing a conductive layer over the barrier layer, and electropolishing the conductive layer while ultrasonically agitating the semiconductor wafer until a predetermined amount of the conductive layer remains over the barrier layer. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括一种用于在半导体晶片上形成电介质层并图案化介电层中的至少一个开口，在电介质层上沉积阻挡层，在阻挡层上沉积导电层和电解抛光导电层，同时超声搅拌半导体晶片，直到预定量的导电层保留在阻挡层上。描述和要求保护其他实施例。

2. 发明授权

US07560380B2 Chemical dissolution of barrier and adhesion layers 失效
标题翻译：隔离层和粘合层的化学溶解
公开(公告)号：US07560380B2
公开(公告)日：2009-07-14
申请号：US11588982
申请日：2006-10-27
申请人： Tatyana N. Andryushchenko , Anne E. Miller
发明人： Tatyana N. Andryushchenko , Anne E. Miller
IPC分类号： H01L21/20
CPC分类号： H01L21/32134 , H01L21/32115 , H01L21/7684 , H01L21/76843 , H01L21/76865
摘要： A method of forming a metal interconnect for an integrated circuit includes depositing a barrier layer on a dielectric layer having a trench formed therein, depositing an adhesion layer on the barrier layer, depositing a metal layer on the adhesion layer, removing the metal layer using a CMP process until at least a portion of the adhesion layer is exposed, and removing portions of the adhesion layer and the barrier layer sited substantially outside of the trench using a dissolution process. The dissolution process applies an electrolyte solution to those portions of the adhesion layer and the barrier layer sited substantially outside of the trench to dissolve and remove them.
摘要翻译：形成用于集成电路的金属互连的方法包括在其上形成有沟槽的电介质层上沉积阻挡层，在阻挡层上沉积粘合层，在粘合层上沉积金属层，使用 CMP工艺，直到暴露粘附层的至少一部分，并且使用溶解过程将粘合层和阻挡层的部分基本上位于沟槽外部。溶解过程将电解质溶液施加到粘附层的那些部分，并且阻挡层基本上位于沟槽外部以溶解并除去它们。

3. 发明授权

US07585760B2 Method for forming planarizing copper in a low-k dielectric 失效
标题翻译：在低k电介质中形成平坦化铜的方法
公开(公告)号：US07585760B2
公开(公告)日：2009-09-08
申请号：US11473738
申请日：2006-06-23
申请人： Tatyana N. Andryushchenko , Anne E. Miller
发明人： Tatyana N. Andryushchenko , Anne E. Miller
IPC分类号： H01L21/4763
CPC分类号： H01L21/76843 , C25F3/02 , H01L21/32115 , H01L21/32134 , H01L21/7684 , H01L21/76865 , H01L21/76873 , H01L21/76874
摘要： Methods of fabricating an interconnect, which fundamentally comprises forming a second conductive film (e.g., aluminum) over first conductive film (e.g., copper) deposited in an opening formed in a dielectric layer (e.g., low-k dielectric). The second conductive film has an ability to reflow to form a planar surface upon a thermal treatment process. Electropolishing is then used to planarize the second and first conductive films, wherein an electrolyte solution selective to remove the first conductive film faster than the second conductive film is used. An interconnect is formed.
摘要翻译：制造互连的方法，其基本上包括在沉积在形成在电介质层（例如低k电介质）中的开口中的第一导电膜（例如，铜）上形成第二导电膜（例如铝）。第二导电膜在热处理过程中具有回流以形成平坦表面的能力。然后使用电抛光来平坦化第二和第一导电膜，其中使用选择性地比第二导电膜更快地去除第一导电膜的电解质溶液。形成互连。

4. 发明申请

US20070298605A1 Method for forming planarizing copper in a low-k dielectric 失效
标题翻译：在低k电介质中形成平坦化铜的方法
公开(公告)号：US20070298605A1
公开(公告)日：2007-12-27
申请号：US11473738
申请日：2006-06-23
申请人： Tatyana N. Andryushchenko , Anne E. Miller
发明人： Tatyana N. Andryushchenko , Anne E. Miller
IPC分类号： H01L21/4763
CPC分类号： H01L21/76843 , C25F3/02 , H01L21/32115 , H01L21/32134 , H01L21/7684 , H01L21/76865 , H01L21/76873 , H01L21/76874
摘要： Methods of fabricating an interconnect, which fundamentally comprises forming a second conductive film (e.g., aluminum) over first conductive film (e.g., copper) deposited in an opening formed in a dielectric layer (e.g., low-k dielectric). The second conductive film has an ability to reflow to form a planar surface upon a thermal treatment process. Electropolishing is then used to planarize the second and first conductive films, wherein an electrolyte solution selective to remove the first conductive film faster than the second conductive film is used. An interconnect is formed.
摘要翻译：制造互连的方法，其基本上包括在沉积在形成在电介质层（例如低k电介质）中的开口中的第一导电膜（例如，铜）上形成第二导电膜（例如铝）。第二导电膜在热处理过程中具有回流以形成平坦表面的能力。然后使用电抛光来平坦化第二和第一导电膜，其中使用选择性地比第二导电膜更快地去除第一导电膜的电解质溶液。形成互连。

5. 发明授权

US07223685B2 Damascene fabrication with electrochemical layer removal 有权
标题翻译：大马士革制造与电化学层去除
公开(公告)号：US07223685B2
公开(公告)日：2007-05-29
申请号：US10602488
申请日：2003-06-23
申请人： Tatyana N. Andryushchenko , Anne E. Miller
发明人： Tatyana N. Andryushchenko , Anne E. Miller
IPC分类号： H01L21/4763 , H01L21/44 , H01L21/461 , H01L21/302
CPC分类号： C25F5/00 , C25F3/02
摘要： The present application discloses process comprising providing a wafer, the wafer comprising an inter-layer dielectric (ILD) having a feature therein, an under-layer deposited on the ILD, and a barrier layer deposited on the under-layer, and a conductive layer deposited in the feature, placing the wafer in an electrolyte, such that at least the barrier layer is immersed in the electrolyte, and applying an electrical potential between the electrode and the wafer. Also disclosed is an apparatus comprising a vessel having an electrolyte therein, a first electrode at least partially immersed in the electrolyte, the first electrode comprising a wafer comprising an inter-layer dielectric (ILD) having a feature therein, an under-layer deposited on the ILD layer, a barrier layer deposited on the under-layer and a conductive layer deposited in the feature, a second electrode at least partially immersed in the electrolyte, and a potential source for applying a potential difference between the first and second electrodes. Other embodiments are also disclosed and claimed.
摘要翻译：本申请公开了包括提供晶片的方法，晶片包括其中具有特征的层间电介质（ILD），沉积在ILD上的底层和沉积在下层上的阻挡层，以及导电层沉积在特征中，将晶片放置在电解质中，使得至少阻挡层浸入电解质中，并在电极和晶片之间施加电位。还公开了一种包括其中具有电解质的容器的装置，至少部分地浸入电解质中的第一电极，第一电极包括包含其中具有特征的层间电介质（ILD）的晶片，下层沉积在 ILD层，沉积在底层上的阻挡层和沉积在特征中的导电层，至少部分浸入电解质中的第二电极和用于施加第一和第二电极之间的电位差的电位源。还公开并要求保护其他实施例。

6. 发明申请

US20080102631A1 Chemical dissolution of barrier and adhesion layers 失效
标题翻译：隔离层和粘合层的化学溶解
公开(公告)号：US20080102631A1
公开(公告)日：2008-05-01
申请号：US11588982
申请日：2006-10-27
申请人： Tatyana N. Andryushchenko , Anne E. Miller
发明人： Tatyana N. Andryushchenko , Anne E. Miller
IPC分类号： H01L21/44 , H01L21/302 , H01L21/461
CPC分类号： H01L21/32134 , H01L21/32115 , H01L21/7684 , H01L21/76843 , H01L21/76865
摘要： A method of forming a metal interconnect for an integrated circuit includes depositing a barrier layer on a dielectric layer having a trench formed therein, depositing an adhesion layer on the barrier layer, depositing a metal layer on the adhesion layer, removing the metal layer using a CMP process until at least a portion of the adhesion layer is exposed, and removing portions of the adhesion layer and the barrier layer sited substantially outside of the trench using a dissolution process. The dissolution process applies an electrolyte solution to those portions of the adhesion layer and the barrier layer sited substantially outside of the trench to dissolve and remove them.
摘要翻译：形成用于集成电路的金属互连的方法包括在其上形成有沟槽的电介质层上沉积阻挡层，在阻挡层上沉积粘合层，在粘合层上沉积金属层，使用 CMP工艺，直到暴露粘附层的至少一部分，并且使用溶解过程将粘合层和阻挡层的部分基本上位于沟槽外部。溶解过程将电解质溶液施加到粘附层的那些部分，并且阻挡层基本上位于沟槽外部以溶解并除去它们。

7. 发明申请

US20070298607A1 Method for copper damascence fill for forming an interconnect 审中-公开
标题翻译：用于形成互连的铜损坏填充方法
公开(公告)号：US20070298607A1
公开(公告)日：2007-12-27
申请号：US11473833
申请日：2006-06-23
申请人： Tatyana N. Andryushchenko , Ebrahim Andideh , Anne E. Miller , Michael McKeag
发明人： Tatyana N. Andryushchenko , Ebrahim Andideh , Anne E. Miller , Michael McKeag
IPC分类号： H01L21/4763 , H01L21/461
CPC分类号： H01L21/76843 , H01L21/32115 , H01L21/32134 , H01L21/76865 , H01L21/76873 , H01L21/76874
摘要： Methods of fabricating an interconnect, which fundamentally comprises etching back on an overhang section formed over a portion of an opening formed in a dielectric layer, said etching back is selected from one of an electropolishing process and chemical etching process, and said etching back removes the overhang section at a controlled etch rate of about 10 Å/sec to 70 Å/sec; and depositing a conductive material into the opening so as to fill the opening and form an interconnect.
摘要翻译：制造互连的方法，其基本上包括在形成在介电层中形成的开口的一部分上形成的突出部上进行回蚀刻，所述蚀刻回选自电抛光工艺和化学蚀刻工艺之一，并且所述蚀刻将去除突出部分以约10埃/秒至70埃/秒的受控蚀刻速率; 以及将导电材料沉积到所述开口中以便填充所述开口并形成互连。

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