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1. 发明申请

US20130052837A1 Apparatus and Methods for Annealing Wafers 有权
标题翻译：退火晶圆的设备和方法
公开(公告)号：US20130052837A1
公开(公告)日：2013-02-28
申请号：US13215909
申请日：2011-08-23
申请人： Yi-Chao Wang , Yu-Chang Lin , Li-Ting Wang , Tai-Chun Huang , Pei-Ren Jeng , Tze-Liang Lee
发明人： Yi-Chao Wang , Yu-Chang Lin , Li-Ting Wang , Tai-Chun Huang , Pei-Ren Jeng , Tze-Liang Lee
IPC分类号： H01L21/268 , B23K26/00
CPC分类号： H01L21/67115 , B23K26/352 , H01L21/2636 , H01L21/268 , H01L21/324
摘要： A method includes performing an anneal on a wafer. The wafer includes a wafer-edge region, and an inner region encircled by the wafer-edge region. During the anneal, a first power applied on a portion of the wafer-edge region is at least lower than a second power for annealing the inner region.
摘要翻译：一种方法包括在晶片上进行退火。晶片包括晶片边缘区域和由晶片边缘区域包围的内部区域。在退火期间，施加在晶片边缘区域的一部分上的第一功率至少低于用于退火内部区域的第二功率。

2. 发明授权

US09337059B2 Apparatus and methods for annealing wafers 有权
标题翻译：用于退火晶圆的设备和方法
公开(公告)号：US09337059B2
公开(公告)日：2016-05-10
申请号：US13215909
申请日：2011-08-23
申请人： Yi-Chao Wang , Yu-Chang Lin , Li-Ting Wang , Tai-Chun Huang , Pei-Ren Jeng , Tze-Liang Lee
发明人： Yi-Chao Wang , Yu-Chang Lin , Li-Ting Wang , Tai-Chun Huang , Pei-Ren Jeng , Tze-Liang Lee
IPC分类号： H01L21/00 , H01L21/324 , H01L21/268 , H01L21/20 , H01L21/36 , H01L21/44
CPC分类号： H01L21/67115 , B23K26/352 , H01L21/2636 , H01L21/268 , H01L21/324
摘要： A method includes performing an anneal on a wafer. The wafer includes a wafer-edge region, and an inner region encircled by the wafer-edge region. During the anneal, a first power applied on a portion of the wafer-edge region is at least lower than a second power for annealing the inner region.
摘要翻译：一种方法包括在晶片上进行退火。晶片包括晶片边缘区域和由晶片边缘区域包围的内部区域。在退火期间，施加在晶片边缘区域的一部分上的第一功率至少低于用于退火内部区域的第二功率。

3. 发明申请

US20100105185A1 REDUCING POLY-DEPLETION THROUGH CO-IMPLANTING CARBON AND NITROGEN 失效
标题翻译：通过共同植入碳和氮减少多重沉降
公开(公告)号：US20100105185A1
公开(公告)日：2010-04-29
申请号：US12259028
申请日：2008-10-27
申请人： Keh-Chiang Ku , Cheng-Lung Hung , Li-Ting Wang , Chien-Hao Chen , Chien-Hao Huang , Wenli Lin , Yu-Chang Lin
发明人： Keh-Chiang Ku , Cheng-Lung Hung , Li-Ting Wang , Chien-Hao Chen , Chien-Hao Huang , Wenli Lin , Yu-Chang Lin
IPC分类号： H01L21/336 , H01L21/4763
CPC分类号： H01L21/28052 , H01L21/26506 , H01L21/26586 , H01L21/28506 , H01L29/1083 , H01L29/665 , H01L29/6659 , H01L29/7833
摘要： A method for forming a semiconductor structure includes providing a semiconductor substrate; forming a gate dielectric layer over the semiconductor substrate; forming a gate electrode layer over the gate dielectric layer; doping carbon and nitrogen into the gate electrode layer; and, after the step of doping carbon and nitrogen, patterning the gate dielectric layer and the gate electrode layer to form a gate dielectric and a gate electrode, respectively.
摘要翻译：一种形成半导体结构的方法包括提供半导体衬底; 在所述半导体衬底上形成栅介电层; 在所述栅极电介质层上形成栅电极层; 将碳和氮掺杂到栅电极层中; 并且在掺杂碳和氮的步骤之后，分别构图栅极电介质层和栅极电极层以形成栅极电介质和栅电极。

4. 发明授权

US08058134B2 Junction profile engineering using staged thermal annealing 有权
标题翻译：接头型材工程采用分段热退火
公开(公告)号：US08058134B2
公开(公告)日：2011-11-15
申请号：US12618052
申请日：2009-11-13
申请人： Li-Ting Wang , Keh-Chiang Ku , Yu-Chang Lin , Nai-Han Cheng , Li-Ping Huang
发明人： Li-Ting Wang , Keh-Chiang Ku , Yu-Chang Lin , Nai-Han Cheng , Li-Ping Huang
IPC分类号： H01L21/336
CPC分类号： H01L21/324 , H01L21/26506 , H01L21/26513 , H01L21/26586 , H01L29/1083 , H01L29/6659 , H01L29/7833
摘要： An annealing method includes performing an activation annealing on a wafer with a peak temperature of greater than about 1200° C., wherein the activation annealing has a first duration; and performing a defect-recovery annealing on the wafer at a defect-recovery temperature lower than the peak temperature for a second duration. The second duration is longer than the first duration. The annealing method includes no additional annealing steps at temperatures greater than about 1200° C., and no room-temperature cooling step exists between the activation annealing and the defect-recovery annealing.
摘要翻译：退火方法包括在峰值温度大于约1200℃的晶片上进行激活退火，其中活化退火具有第一持续时间; 以及在低于所述峰值温度的缺陷恢复温度下对所述晶片进行缺陷恢复退火，持续第二持续时间。第二个持续时间比第一个持续时间长。退火方法在大于约1200℃的温度下不包括额外的退火步骤，并且在活化退火和缺陷恢复退火之间不存在室温冷却步骤。

5. 发明申请

US20100210086A1 Junction Profile Engineering Using Staged Thermal Annealing 有权
标题翻译：接头型材工程使用分段热退火
公开(公告)号：US20100210086A1
公开(公告)日：2010-08-19
申请号：US12618052
申请日：2009-11-13
申请人： Li-Ting Wang , Keh-Chiang Ku , Yu-Chang Lin , Nai-Han Cheng , Li-Ping Huang
发明人： Li-Ting Wang , Keh-Chiang Ku , Yu-Chang Lin , Nai-Han Cheng , Li-Ping Huang
IPC分类号： H01L21/336
CPC分类号： H01L21/324 , H01L21/26506 , H01L21/26513 , H01L21/26586 , H01L29/1083 , H01L29/6659 , H01L29/7833
摘要： An annealing method includes performing an activation annealing on a wafer with a peak temperature of greater than about 1200° C., wherein the activation annealing has a first duration; and performing a defect-recovery annealing on the wafer at a defect-recovery temperature lower than the peak temperature for a second duration. The second duration is longer than the first duration. The annealing method includes no additional annealing steps at temperatures greater than about 1200° C., and no room-temperature cooling step exists between the activation annealing and the defect-recovery annealing.
摘要翻译：退火方法包括在峰值温度大于约1200℃的晶片上进行激活退火，其中活化退火具有第一持续时间; 以及在低于所述峰值温度的缺陷恢复温度下对所述晶片进行缺陷恢复退火，持续第二持续时间。第二个持续时间比第一个持续时间长。退火方法在大于约1200℃的温度下不包括额外的退火步骤，并且在活化退火和缺陷恢复退火之间不存在室温冷却步骤。

6. 发明授权

US07736968B2 Reducing poly-depletion through co-implanting carbon and nitrogen 失效
标题翻译：通过共同植入碳和氮来减少多元消耗
公开(公告)号：US07736968B2
公开(公告)日：2010-06-15
申请号：US12259028
申请日：2008-10-27
申请人： Keh-Chiang Ku , Cheng-Lung Hung , Li-Ting Wang , Chien-Hao Chen , Chien-Hao Huang , Wenli Lin , Yu-Chang Lin
发明人： Keh-Chiang Ku , Cheng-Lung Hung , Li-Ting Wang , Chien-Hao Chen , Chien-Hao Huang , Wenli Lin , Yu-Chang Lin
IPC分类号： H01L21/8238
CPC分类号： H01L21/28052 , H01L21/26506 , H01L21/26586 , H01L21/28506 , H01L29/1083 , H01L29/665 , H01L29/6659 , H01L29/7833
摘要： A method for forming a semiconductor structure includes providing a semiconductor substrate; forming a gate dielectric layer over the semiconductor substrate; forming a gate electrode layer over the gate dielectric layer; doping carbon and nitrogen into the gate electrode layer; and, after the step of doping carbon and nitrogen, patterning the gate dielectric layer and the gate electrode layer to form a gate dielectric and a gate electrode, respectively.
摘要翻译：一种形成半导体结构的方法包括提供半导体衬底; 在所述半导体衬底上形成栅介电层; 在所述栅极电介质层上形成栅电极层; 将碳和氮掺杂到栅电极层中; 并且在掺杂碳和氮的步骤之后，分别构图栅极电介质层和栅极电极层以形成栅极电介质和栅电极。

7. 发明申请

US20180051451A1 ACTIVATION SYSTEM FOR ELECTRONIC URINAL 审中-公开
公开(公告)号：US20180051451A1
公开(公告)日：2018-02-22
申请号：US15239910
申请日：2016-08-18
申请人： Hsiang-Hung Wang , Yu-Chang Lin
发明人： Hsiang-Hung Wang , Yu-Chang Lin
IPC分类号： E03D5/10 , E03D13/00
CPC分类号： E03D5/105 , E03D13/00
摘要： An activation system for electronic urinal comprises a urinal fluidly communicated with an inlet pipe and a control unit arranged between the urinal and the inlet pipe. The control unit includes a solenoid valve, a sensor, and a power supply. The solenoid valve is used for controlling to water or seal. The sensor is electrically connected to the solenoid valve. The power supply provides power to the solenoid valve and the sensor. The control unit has an activation switch which is electrically connected to the solenoid valve. The activation switch has a wireless transmission module and a timing controller for turning off the wireless transmission module. The activation switch is pressed so that the wireless transmission module is activated to set water discharge and a turn-off time of the solenoid valve and is turned off after a preset time counted by the time controller to save power.

8. 发明授权

US07652290B2 Standby current erasion circuit of DRAM 有权
标题翻译： DRAM的待机电流擦除电路
公开(公告)号：US07652290B2
公开(公告)日：2010-01-26
申请号：US10232460
申请日：2002-08-30
申请人： Yu-Chang Lin
发明人： Yu-Chang Lin
IPC分类号： H01L27/108 , G11C29/04 , G11C29/12 , G11C29/50 , G11C8/08 , G11C8/10 , G11C8/14 , G11C7/12 , G11C7/18
CPC分类号： G11C11/4085 , G11C2207/2227
摘要： The present invention discloses a standby current erasion circuit applied in DRAM, which improves prior art word line driving circuit to have the word line voltage outputted in standby mode be equal to the bit line voltage, thereby the short DC standby current between the word line and bit line can be erased.
摘要翻译：本发明公开了一种应用在DRAM中的待机电流擦除电路，其改进了现有技术的字线驱动电路，使待机模式下输出的字线电压等于位线电压，从而在字线和位线可以被擦除。

9. 发明申请

US20080174923A1 ESD protection scheme for semiconductor devices having dummy pads 审中-公开
公开(公告)号：US20080174923A1
公开(公告)日：2008-07-24
申请号：US11812221
申请日：2007-06-15
申请人： Yi-Hsun Wu , Yan-Chih Jiang , Yu-Chang Lin , Jian-Hsing Lee
发明人： Yi-Hsun Wu , Yan-Chih Jiang , Yu-Chang Lin , Jian-Hsing Lee
IPC分类号： H02H9/00 , H01L21/336
CPC分类号： H01L27/0255
摘要： A semiconductor device formed in a semiconductor substrate for dissipating electrostatic discharge and/or accumulated charge in an integrated circuit is provided. In one embodiment, the device comprises a semiconductor substrate; a plurality of layers of metal lines formed overlying the substrate; a plurality of via plugs through intermetal dielectric layers between the layers of metal lines and wherein the via plugs interconnect the metal lines; and a dummy pad formed over the plurality of layers of metal lines, the dummy pad having a diode connected thereto and to ground for providing a discharge path for the electrostatic discharge and/or accumulated charge.

10. 发明授权

US07189586B2 Test key for monitoring gate conductor to deep trench misalignment 有权
标题翻译：测试键用于监控栅极导体与深沟槽的未对准
公开(公告)号：US07189586B2
公开(公告)日：2007-03-13
申请号：US10904652
申请日：2004-11-21
申请人： Yu-Chang Lin
发明人： Yu-Chang Lin
IPC分类号： H01L21/66 , H01L23/58
CPC分类号： H01L22/34 , Y10S257/905 , Y10S257/908
摘要： A test key for monitoring GC-DT misalignment is provided. Deep trench capacitors are embedded in an interlacing matrix manner. GC lines are defined on a substrate and passing over the deep trench capacitors. A first bit line contact pattern surrounded by first assistant bit line contact patterns is disposed on the right side of a first deep trench capacitor. A second bit line contact pattern surrounded by second assistant bit line contact patterns is disposed on the left side of a second deep trench capacitor. The test key has a mirror symmetric line. The first assistant bit line contact patterns and second assistant bit line contact patterns are symmetric with respect to the mirror symmetric line. An active area connects the first bit line contact pattern and the second bit line contact pattern. A signal-in bit line is connected to the first bit line contact and a signal-out bit line is connected to the second bit line contact. The rest rows of the bit lines are dummy bit lines and floating.
摘要翻译：提供了一个用于监测GC-DT不对准的测试键。深沟槽电容器以隔行矩阵的方式嵌入。 GC线定义在衬底上并穿过深沟槽电容器。由第一辅助位线接触图案包围的第一位线接触图案设置在第一深沟槽电容器的右侧。由第二辅助位线接触图案包围的第二位线接触图案设置在第二深沟槽电容器的左侧。测试键具有镜像对称线。第一辅助位线接触图案和第二辅助位线接触图案相对于镜像对称线对称。有源区域连接第一位线接触图案和第二位线接触图案。信号输入位线连接到第一位线触点，并且信号输出位线连接到第二位线触点。位线的其余行是虚拟位线和浮动。

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