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1. 发明公开

CN1487564A 电子装置用衬底、电子装置用衬底的制造方法、及电子装置失效
公开(公告)号：CN1487564A
公开(公告)日：2004-04-07
申请号：CN03156519.0
申请日：2003-09-03
申请人：精工爱普生株式会社
发明人：樋口天光 , 岩下节也 , 宫泽弘
IPC分类号： H01L21/08
CPC分类号： H01L21/31691 , H01L21/32058 , H01L28/55 , H01L28/60 , H01L41/316 , H01L41/332
摘要：本发明提供了一种电子装置用衬底，其中在衬底上形成重新构成表面或氢封端表面的处理不再是必要的，并且在衬底上形成的缓冲层是沿(100)取向外延生长的，以及一种该衬底的制造方法。电子装置用衬底100包括：由硅构成的衬底11，和在衬底11形成薄膜表面上层压外延生成的具有萤石结构的第一缓冲层12和第二缓冲层13，具有分层的钙钛矿结构的第一氧化物电极层14，具有简单钙钛矿结构的第二氧化物电极层15。通过在SiO升华区在自然氧化物薄膜上照射金属等离子体，使得第一缓冲层12的外延生长速率高于SiO2的生成速率。

2. 发明授权

CN1260774C 铁电体元件或压电体元件用衬底及其制造方法及功能元件失效
公开(公告)号：CN1260774C
公开(公告)日：2006-06-21
申请号：CN03156519.0
申请日：2003-09-03
申请人：精工爱普生株式会社
发明人：樋口天光 , 岩下节也 , 宫泽弘
IPC分类号： H01L21/08
CPC分类号： H01L21/31691 , H01L21/32058 , H01L28/55 , H01L28/60 , H01L41/316 , H01L41/332
摘要：本发明提供了一种电子装置用衬底，其中在衬底上形成重新构成表面或氢封端表面的处理不再是必要的，并且在衬底上形成的缓冲层是沿(100)取向外延生长的，以及一种该衬底的制造方法。电子装置用衬底100包括：由硅构成的衬底11，和在衬底11形成薄膜表面上层压外延生成的具有萤石结构的第一缓冲层12和第二缓冲层13，具有分层的钙钛矿结构的第一氧化物电极层14，具有简单钙钛矿结构的第二氧化物电极层15。通过在SiO升华区在自然氧化物薄膜上照射金属等离子体，使得第一缓冲层12的外延生长速率高于SiO2的生成速率。

3. 发明授权

US06960539B2 Substrate for electronic devices, manufacturing method therefor, and electronic device 失效
标题翻译：电子器件基板，其制造方法和电子器件
公开(公告)号：US06960539B2
公开(公告)日：2005-11-01
申请号：US10644989
申请日：2003-08-21
申请人： Takamitsu Higuchi , Setsuya Iwashita , Hiromu Miyazawa
发明人： Takamitsu Higuchi , Setsuya Iwashita , Hiromu Miyazawa
IPC分类号： C23C16/40 , H01L21/02 , H01L21/316 , H01L21/3205 , H01L21/8246 , H01L27/105 , H01L41/08 , H01L41/22 , H01L41/29 , H01L21/31
CPC分类号： H01L21/31691 , H01L21/32058 , H01L28/55 , H01L28/60 , H01L41/316 , H01L41/332
摘要： There is provided a substrate for electronic devices, in which treatment for forming a reconstructed surface or a hydrogen-terminated surface on a substrate is not necessary, and a buffer layer formed on the substrate can be epitaxially grown in the (100) orientation, and a manufacturing method therefor. The substrate 100 for electronic devices comprises; a substrate 11 consisting of silicon, and a first buffer layer 12 and a second buffer layer 13 having a fluorite structure, a first oxide electrode layer 14 having a layered perovskite structure, and a second oxide electrode layer 15 having a simple perovskite structure, which are epitaxially grown and laminated in this order on a film-forming surface of the substrate 11. The first buffer layer 12 is grown epitaxially at a higher rate than the growth rate of SiO2, by irradiating a metallic plasma onto a natural oxide film in an SiO sublimation area.
摘要翻译：提供了一种用于电子器件的衬底，其中不需要在衬底上形成重构表面或氢封端表面的处理，并且可以以（100）取向外延生长衬底上的缓冲层，并且其制造方法。电子设备用基板100包括：由硅组成的基板11，具有萤石结构的第一缓冲层12和第二缓冲层13，具有层状钙钛矿结构的第一氧化物电极层14和具有简单的钙钛矿结构的第二氧化物电极层15，在基板11的成膜表面上以该顺序外延生长并层压。通过照射金属的第一缓冲层12以比SiO 2的生长速率更高的速度外延生长第一缓冲层12。将等离子体加入到SiO升华区的自然氧化膜上。

4. 发明申请

US20190214474A1 METHOD FOR FORMING A QUBIT DEVICE 审中-公开
公开(公告)号：US20190214474A1
公开(公告)日：2019-07-11
申请号：US16222911
申请日：2018-12-17
申请人： IMEC vzw
发明人： Clement Merckling , Nadine Collaert
IPC分类号： H01L29/43 , H01L21/3205 , H01L21/285 , H01L21/28 , H01L21/306 , H01L21/308 , H01L21/02 , H01L29/66 , H01L29/06 , H01L29/423 , H01L29/417 , H01L29/786 , G06N10/00
CPC分类号： H01L29/437 , B82Y10/00 , G06N10/00 , H01L21/02546 , H01L21/02549 , H01L21/02603 , H01L21/28264 , H01L21/28575 , H01L21/30612 , H01L21/308 , H01L21/32058 , H01L29/0673 , H01L29/0847 , H01L29/413 , H01L29/41733 , H01L29/42356 , H01L29/42384 , H01L29/66522 , H01L29/66742 , H01L29/66977 , H01L29/7613 , H01L29/78681 , H01L29/78696
摘要： The disclosed technology is directed to a method of forming a qubit device. In one aspect, the method comprises: forming a gate electrode embedded in an insulating layer formed on a substrate, wherein an upper surface of the substrate is formed from a group IV semiconductor material and the gate electrode extends along the substrate in a first horizontal direction; forming an aperture in the insulating layer, the aperture exposing a portion of the substrate; forming, in an epitaxial growth process, a semiconductor structure comprising a group III-V semiconductor substrate contact part and a group III-V semiconductor disc part, the substrate contact part having a bottom portion abutting the portion of the substrate and an upper portion protruding from the aperture above an upper surface of the insulating layer, the semiconductor disc part extending from the upper portion of the substrate contact part, horizontally along the upper surface of the insulating layer to overlap a portion of the gate electrode; forming a mask covering a portion of the disc part, the portion of the disc part extending across the portion of the gate electrode in a second horizontal direction; etching regions of the semiconductor structure exposed by the mask such that the masked portion of the disc part remains to form a channel structure extending across the portion of the gate electrode; and forming a superconductor source contact and a superconductor drain contact on the channel structure at opposite sides of the portion of the gate electrode.

5. 发明授权

US5851843A Method of manufacturing a super conduction field effect transistor 失效
标题翻译：制造超导电场效应晶体管的方法
公开(公告)号：US5851843A
公开(公告)日：1998-12-22
申请号：US951503
申请日：1997-10-16
申请人： Jeong Dae Suh , Gun Yong Sung
发明人： Jeong Dae Suh , Gun Yong Sung
IPC分类号： C30B29/22 , H01L21/3205 , H01L39/00 , H01L39/14 , H01L39/22 , H01L39/24 , H01L21/00
CPC分类号： H01L39/146 , H01L21/32058
摘要： A method of manufacturing super conduction field effect transistor having a bi-crystal boundary junction is disclosed. According to the present invention, it is constituted such that on a SrTiO.sub.3 bi-crystal substrate, a bi-crystal super conductive thin films for source and drain electrode having a compound of YBa.sub.2 Cu.sub.3 O.sub.7-x, a non-super conductive oxide layer having a compound of PrBa.sub.2 Cu.sub.3 O.sub.7-x interposed between the bi-crystal super conductive thin films for source and drain electrode and the SrTiO.sub.3 bi-crystal substrate, a boundary channel interposed therebetween, a amorphous insulating layer for gate electrode having a compound of SrTiO.sub.3 deposited on a portion between the bi-crystal super conductive thin films for source and drain electrode above the boundary channel, metal pads for electrode, respectively, formed on the bi-crystal super conductive thin films for source and drain electrode and the amorphous insulating layer for gate electrode are sequentially formed.
摘要翻译：公开了一种制造具有双晶边界结的超导电场效应晶体管的方法。根据本发明，其结构使得在SrTiO3双晶基板上具有具有YBa2Cu3O7-x的化合物的源极和漏极的双晶超导电薄膜，具有化合物的非超导导电氧化物层 PrBa2Cu3O7-x介于用于源极和漏极的双晶超导电薄膜和SrTiO3双晶衬底之间，边界通道介于其间，用于栅电极的非晶绝缘层，其中沉积有SrTiO 3的化合物沉积在用于源极和漏极的双晶超级导电薄膜和用于栅电极的非晶绝缘层上分别形成的用于源极和漏电极的双晶超级导电薄膜，分别用于电极的金属焊盘，栅电极的非晶绝缘层形成。

6. 发明申请

US20190089033A1 MICROFABRICATED AIR BRIDGES FOR PLANAR MICROWAVE RESONATOR CIRCUITS 审中-公开
公开(公告)号：US20190089033A1
公开(公告)日：2019-03-21
申请号：US15705303
申请日：2017-09-15
申请人： International Business Machines Corporation
发明人： Vivekananda P. Adiga , Markus Brink
IPC分类号： H01P3/02 , H01P11/00 , H01B12/06
CPC分类号： H01P3/026 , H01B12/06 , H01L21/32058 , H01L21/76891 , H01L23/4821 , H01P11/003 , H05H7/20
摘要： The present invention provides a process and structure of microfabricated air bridges for planar microwave resonator circuits. In an embodiment, the invention includes depositing a superconducting film on a surface of a base material, where the superconducting film is formed with a compressive stress, where the compressive stress is higher than a critical buckling stress of a defined structure, etching an exposed area of the superconducting film, thereby creating the at least one bridge, etching the base material, thereby forming a gap between the at least one bridge and the base material, depositing the at least one metal line on at least part of the superconducting film and at least part of the base material, where the at least one metal line runs under the bridge.

7. 发明申请

US20050167715A1 Substrate for electronic devices, manufacturing method therefor, and electronic device 审中-公开
标题翻译：电子器件基板，其制造方法和电子器件
公开(公告)号：US20050167715A1
公开(公告)日：2005-08-04
申请号：US11094665
申请日：2005-03-31
申请人： Takamitsu Higuchi , Setsuya Iwashita , Hiromu Miyazawa
发明人： Takamitsu Higuchi , Setsuya Iwashita , Hiromu Miyazawa
IPC分类号： C23C16/40 , H01L21/02 , H01L21/316 , H01L21/3205 , H01L21/8246 , H01L27/105 , H01L41/08 , H01L41/22 , H01L41/29 , H01L29/76
CPC分类号： H01L21/02194 , H01L21/022 , H01L21/02293 , H01L21/02301 , H01L21/02312 , H01L21/02315 , H01L21/31691 , H01L21/32058 , H01L28/55 , H01L28/60 , H01L41/316 , H01L41/332
摘要： There is provided a substrate for electronic devices, in which treatment for forming a reconstructed surface or a hydrogen-terminated surface on a substrate is not necessary, and a buffer layer formed on the substrate can be epitaxially grown in the (100) orientation, and a manufacturing method therefor. The substrate 100 for electronic devices comprises; a substrate 11 consisting of silicon, and a first buffer layer 12 and a second buffer layer 13 having a fluorite structure, a first oxide electrode layer 14 having a layered perovskite structure, and a second oxide electrode layer 15 having a simple perovskite structure, which are epitaxially grown and laminated in this order on a film-forming surface of the substrate 11. The first buffer layer 12 is grown epitaxially at a higher rate than the growth rate of SiO2, by irradiating a metallic plasma onto a natural oxide film in an SiO sublimation area.
摘要翻译：提供了一种用于电子器件的衬底，其中不需要在衬底上形成重构表面或氢封端表面的处理，并且可以以（100）取向外延生长衬底上的缓冲层，并且其制造方法。电子设备用基板100包括：由硅组成的基板11，具有萤石结构的第一缓冲层12和第二缓冲层13，具有层状钙钛矿结构的第一氧化物电极层14和具有简单的钙钛矿结构的第二氧化物电极层15，在基板11的成膜表面上依次外延生长并层叠。通过在SiO升华区域中的金属等离子体上照射到天然氧化物膜上，以比SiO 2的生长速度更高的速度外延生长第一缓冲层12。

8. 发明授权

US09577177B1 System and method for fabricating super conducting circuitry on both sides of an ultra-thin layer 有权
标题翻译：在超薄层的两侧制造超导电路的系统和方法
公开(公告)号：US09577177B1
公开(公告)日：2017-02-21
申请号：US15164365
申请日：2016-05-25
申请人： The United States of America as represented by the Administrator of the National Aeronautics and Space Administration
发明人： Ari D. Brown , Vilem Mikula
IPC分类号： H01L39/24
CPC分类号： H01L23/53285 , H01L21/32058 , H01L21/743 , H01L21/76891
摘要： A method of fabricating circuitry in a wafer includes depositing a superconducting metal on a silicon on insulator wafer having a handle wafer, coating the wafer with a sacrificial layer and bonding the wafer to a thermally oxide silicon wafer with a first epoxy. The method includes flipping the wafer, thinning the flipped wafer by removing a handle wafer, etching a buried oxide layer, depositing a superconducting layer, bonding the wafer to a thermally oxidized silicon wafer having a handle wafer using an epoxy, flipping the wafer again, thinning the flipped wafer, etching a buried oxide layer from the wafer and etching the sacrificial layer from the wafer. The result is a wafer having superconductive circuitry on both sides of an ultra-thin silicon layer.
摘要翻译：一种在晶片中制造电路的方法包括在具有处理晶片的硅绝缘体晶片上沉积超导金属，用牺牲层涂覆晶片，并将晶片与第一环氧树脂结合到热氧化硅晶片。该方法包括翻转晶片，通过去除处理晶片，蚀刻掩埋氧化物层，沉积超导层，将晶片与使用环氧树脂的处理晶片接合的热氧化硅晶片，再次翻转晶片，从而使翻转的晶片变薄，使翻转的晶片变薄，从晶片上蚀刻掩埋氧化物层并从晶片上蚀刻牺牲层。结果是在超薄硅层的两侧具有超导电路的晶片。

9. 发明申请

US20040053460A1 Substrate for electronic devices, manufacturing method therefor, and electronic device 失效
标题翻译：电子器件基板，其制造方法和电子器件
公开(公告)号：US20040053460A1
公开(公告)日：2004-03-18
申请号：US10644989
申请日：2003-08-21
申请人： SEIKO EPSON CORPORATION
发明人： Takamitsu Higuchi , Setsuya Iwashita , Hiromu Miyazawa
IPC分类号： H01L021/8238
CPC分类号： H01L21/31691 , H01L21/32058 , H01L28/55 , H01L28/60 , H01L41/316 , H01L41/332
摘要： There is provided a substrate for electronic devices, in which treatment for forming a reconstructed surface or a hydrogen-terminated surface on a substrate is not necessary, and a buffer layer formed on the substrate can be epitaxially grown in the (100) orientation, and a manufacturing method therefor. The substrate 100 for electronic devices comprises; a substrate 11 consisting of silicon, and a first buffer layer 12 and a second buffer layer 13 having a fluorite structure, a first oxide electrode layer 14 having a layered perovskite structure, and a second oxide electrode layer 15 having a simple perovskite structure, which are epitaxially grown and laminated in this order on a film-forming surface of the substrate 11. The first buffer layer 12 is grown epitaxially at a higher rate than the growth rate of SiO2, by irradiating a metallic plasma onto a natural oxide film in an SiO sublimation area.
摘要翻译：提供了一种用于电子器件的衬底，其中不需要在衬底上形成重构表面或氢封端表面的处理，并且可以以（100）取向外延生长衬底上的缓冲层，并且其制造方法。电子设备用基板100包括：由硅组成的基板11和具有萤石结构的第一缓冲层12和第二缓冲层13，具有层状钙钛矿结构的第一氧化物电极层14和具有简单的钙钛矿结构的第二氧化物电极层15，在衬底11的成膜表面上以此顺序外延生长并层压。通过将金属等离子体照射到天然氧化物膜上，以比SiO 2的生长速率更高的速度外延生长第一缓冲层12 SiO升华区。

10. 发明公开

EP0323342A2 A semiconductor substrate having a superconducting thin film 失效
标题翻译： Ein Halbleitersubstrat mit einem supraleitendenDünnfilm。
公开(公告)号：EP0323342A2
公开(公告)日：1989-07-05
申请号：EP88403324.2
申请日：1988-12-26
申请人： SUMITOMO ELECTRIC INDUSTRIES LIMITED
发明人： Itozaki, Hideo Itami Works of Sumitomo , Harada, Keizo Itami Works of Sumitomo , Fujimori, Naoji Itami Works of Sumitomo , Yazu, Shuji Itami Works of Sumitomo , Jodai, Tetsuji Itami Works of Sumitomo
IPC分类号： H01L39/12 , H01L39/24
CPC分类号： H01L39/143 , H01L21/0242 , H01L21/02491 , H01L21/02502 , H01L21/02521 , H01L21/02546 , H01L21/32058 , H01L21/76891 , H01L23/53285 , H01L39/247 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor substrate comprising an oxide substrate such as MgO or SrTiO₃, a superconducting thin film layer composed of compound oxide such as Ln₁Ba₂Cu₃O 7-δ (Ln is lanthanide) and deposited on said oxide substrate, and a semiconductor layer composed of compound semiconductor material such as GaAs and deposited on said superconducting thin film layer.
摘要翻译：包括诸如MgO或SrTiO 3的氧化物衬底的半导体衬底，由诸如Ln1Ba2Cu3O7-δ（Ln是镧系元素）的复合氧化物构成并沉积在所述氧化物衬底上的超导薄膜层以及由化合物半导体材料 GaAs并沉积在所述超导薄膜层上。

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