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1. 发明公开

CN1655457A 分数分频电路和使用它的数据传输装置无效
公开(公告)号：CN1655457A
公开(公告)日：2005-08-17
申请号：CN200510007868.5
申请日：2005-02-06
申请人：恩益禧电子股份有限公司
发明人：佐伯贵范
IPC分类号： H03L7/08 , H03K23/00
CPC分类号： H03K23/546 , H03L7/1974
摘要：提供一种电路规模小、输出占空比50％的时钟的分数分频电路和包括该分频电路的数据传输装置。分数分频电路具有：整数分频电路，由多个主从触发器构成，以分频比1/N(N是整数)对时钟信号进行分频；和逻辑电路，输入从上述主从触发器的主段和从段输出的多个信号，输出以分频比2/N对上述时钟信号进行分频而得到的占空比50％的信号。数据传输装置构成为：可按每个信道来切换PLL的输出的倍增时钟和用分数分频电路对倍增时钟进行分频而得到的时钟。

2. 发明公开

CN102684682A 用于提供正交输出信号的分频设备和方法失效
公开(公告)号：CN102684682A
公开(公告)日：2012-09-19
申请号：CN201210044571.6
申请日：2012-01-04
申请人：英特尔移动通信有限公司
发明人： J·霍尔茨莱特纳 , W·舍尔姆鲍尔
IPC分类号： H03K21/00
CPC分类号： H03B19/00 , H03B27/00 , H03K23/546
摘要：提供正交输出信号的分频设备和方法。分频设备具有用于提供具有基本信号频率的基本信号的信号源；具有第一分频比的第一整数正交分频器，用于接收基本信号和用于提供具有相应于第一整数正交分频器的第一分频比的第一正交信号频率的第一正交信号；正交混频设备，用于提供仅基于第一正交混频输入信号和第二正交混频输入信号的正交混频输出信号，其中第一正交混频输入信号相应于第一正交信号；整数正交分频设备，包括具有第二分频比的第二整数正交分频器，用于接收正交混频输出信号或者同频率的从正交混频输出信号中导出的信号以及用于提供第二正交混频输出信号和正交输出信号，其中第二正交混频输入信号从正交输出信号中导出或者相应于它。

3. 发明授权

CN102684682B 用于提供正交输出信号的分频设备和方法失效
公开(公告)号：CN102684682B
公开(公告)日：2015-09-30
申请号：CN201210044571.6
申请日：2012-01-04
申请人：英特尔移动通信有限公司
发明人： J·霍尔茨莱特纳 , W·舍尔姆鲍尔
IPC分类号： H03K21/00
CPC分类号： H03B19/00 , H03B27/00 , H03K23/546
摘要：提供正交输出信号的分频设备和方法。分频设备具有用于提供具有基本信号频率的基本信号的信号源；具有第一分频比的第一整数正交分频器，用于接收基本信号和用于提供具有相应于第一整数正交分频器的第一分频比的第一正交信号频率的第一正交信号；正交混频设备，用于提供仅基于第一正交混频输入信号和第二正交混频输入信号的正交混频输出信号，其中第一正交混频输入信号相应于第一正交信号；整数正交分频设备，包括具有第二分频比的第二整数正交分频器，用于接收正交混频输出信号或者同频率的从正交混频输出信号中导出的信号以及用于提供第二正交混频输出信号和正交输出信号，其中第二正交混频输入信号从正交输出信号中导出或者相应于它。

4. 发明公开

EP1562294A1 Fractional frequency divider circuit and data transmission apparatus using the same 有权
标题翻译：用破碎分频比和一个数据传输设备分频器使用这种分频器
公开(公告)号：EP1562294A1
公开(公告)日：2005-08-10
申请号：EP05002703.6
申请日：2005-02-08
申请人： NEC Electronics Corporation
发明人： Saeki, Takanori c/o NEC Electronics Corporation
IPC分类号： H03L7/197 , H03K21/02
CPC分类号： H03K23/546 , H03L7/1974
摘要： A fractional frequency divider circuit with a small circuit scale that outputs a clock with a duty ratio of 50%, and a data transmission apparatus comprising same. The fractional frequency divider circuit is constituted by multiple master-slave flip-flops, and comprises an integer frequency divider circuit that frequency-divides a clock signal with a frequency-division ratio of 1/N (N is an integer), and a logic circuit into which multiple signals outputted from master stages and slave stages of the master-slave flip-flops are inputted and that outputs a signal with a duty ratio of 50% obtained by frequency-dividing the clock signal with a frequency-division ratio of 2/N. The data transmission apparatus is constituted such that it is possible to switch over between a frequency-multiplied clock outputted by a PLL and a clock obtained by frequency-dividing the frequency-multiplied clock with the fractional frequency divider circuit for each channel.
摘要翻译：用小的电路规模甲分数分频器电路做输出具有50％的占空比，和一个数据发送装置，包括相同的时钟。分数分频电路由多个主从构成触发器，和整数分频电路的包括没有分频为1 / N（N为整数）分频比的时钟信号，和一个逻辑电路成多个信号，从主从的主级和从属级所输出的触发器被输入并做输出由获得的50％的占空比的信号分频的时钟信号为2的分频比 / N。所述数据传输装置的构成做了检查，可以一个倍频时钟由PLL的输出，并且被分频以对每个通道的分数分频器电路的频率倍增时钟获得的时钟之间切换。

5. 发明申请

US20060114031A1 Fractional-integer phase-locked loop system with a fractional-frequency-interval phase frequency detector 有权
$Fractional-integer phase-locked loop system with a fractional-frequency-interval phase frequency detector$
公开(公告)号：US20060114031A1
公开(公告)日：2006-06-01
申请号：US11331638
申请日：2006-01-13
申请人： John Melanson
发明人： John Melanson
IPC分类号： H03D13/00
CPC分类号： H03K23/68 , H03K23/546
摘要： A phase-locked loop circuit has a fractional-frequency-interval phase frequency detector, a charge pump, an oscillator, and a divider. The fractional-frequency-interval phase frequency detector has a phase frequency detector unit that is utilized as or comprises a plurality of phase frequency detector units. The divider is responsive to the oscillator and provides divider values for dividing an oscillator frequency by the divider values to provide a feedback frequency of a feedback loop signal of the phase-locked loop circuit. A reference input frequency is input as a first input into the phase frequency detector unit. The feedback frequency is input and selectively delayed as second inputs into the phase frequency detector unit so that the second inputs are aligned for input according to the reference input frequency and an oscillator frequency is, in effect, responsive to the phase frequency detector units and allowed to be divided by a fractional-integer divider value.

6. 发明授权

US07049852B2 Fractional-integer phase-locked loop system with a fractional-frequency-interval phase frequency detector 有权
$Fractional-integer phase-locked loop system with a fractional-frequency-interval phase frequency detector$
标题翻译：具有分数 - 频间隔相位频率检测器的分数整数锁相环系统
公开(公告)号：US07049852B2
公开(公告)日：2006-05-23
申请号：US10770186
申请日：2004-02-02
申请人： John L. Melanson
发明人： John L. Melanson
IPC分类号： H03K21/00
CPC分类号： H03K23/68 , H03K23/546
摘要： A phase-locked loop circuit has a fractional-frequency-interval phase frequency detector, a charge pump, an oscillator, and a divider. The fractional-frequency-interval phase frequency detector has a phase frequency detector unit that is utilized as or comprises a plurality of phase frequency detector units. The divider is responsive to the oscillator and provides divider values for dividing an oscillator frequency by the divider values to provide a feedback frequency of a feedback loop signal of the phase-locked loop circuit. A reference input frequency is input as a first input into the phase frequency detector unit. The feedback frequency is input and selectively delayed as second inputs into the phase frequency detector unit so that the second inputs are aligned for input according to the reference input frequency and an oscillator frequency is, in effect, responsive to the phase frequency detector units and allowed to be divided by a fractional-integer divider value.
摘要翻译：锁相环电路具有分频间隔相位频率检测器，电荷泵，振荡器和分频器。分数 - 频率间隔相位频率检测器具有用作多个相位频率检测器单元或由多个相位频率检测器单元使用的相位频率检测器单元。分频器响应于振荡器，并提供用于将振荡器频率除以分频值的分频器值，以提供锁相环电路的反馈环路信号的反馈频率。参考输入频率作为第一输入输入到相位频率检测器单元中。反馈频率作为第二输入被输入并选择性地延迟到相位频率检测器单元中，使得第二输入根据参考输入频率对准输入，并且振荡器频率实际上响应于相位频率检测器单元并允许由分数整数除法器值除。

7. 发明申请

US20020057117A1 Frequency dividing circuit 有权
标题翻译：分频电路
公开(公告)号：US20020057117A1
公开(公告)日：2002-05-16
申请号：US09982844
申请日：2001-10-22
发明人： Ka Lun Choi , Derek Hing Sang Tam
IPC分类号： H03K021/00
CPC分类号： H03K23/546
摘要： A frequency dividing circuit divides a master clock frequency by a non-integer factor to provide an output clock signal whose frequency is equal to the frequency of the master clock signal divided by that non-integer factor. In one embodiment, the circuit is operative to divide the master clock frequency by 2.5.
摘要翻译：分频电路将主时钟频率除以非整数因子以提供其频率等于主时钟信号的频率除以该非整数因子的输出时钟信号。在一个实施例中，该电路用于将主时钟频率除以2.5。

8. 发明申请

WO2007109743A3 FREQUENCY DIVIDER 审中-公开
标题翻译：频率分配器
公开(公告)号：WO2007109743A3
公开(公告)日：2008-05-08
申请号：PCT/US2007064562
申请日：2007-03-21
申请人： MULTIGIG INC , WOOD JOHN
发明人： WOOD JOHN
IPC分类号： H04B1/00
CPC分类号： H03L7/0995 , H03K23/54 , H03K23/546 , H03L7/0998
摘要： A frequency divider using a clock source with a plurality of phase signals of a multi-phase oscillator. In one version, the divider includes a plurality of spot-moving stages that are connected to form a ring. Spot-moving stages are stages that advance a one or a zero, while clearing the previous stage. Depending on the number of stages and the number of phases of the clock to advance a spot through all of the stages, a divider ratio is determined. In another embodiment, a plurality of latch elements is provided with a divided input and each is re-clocked with the phases of a multi-phase oscillator. The outputs of the latch elements are combined in a capacitor array to create the output waveform. An interpolator useful in conjunction with a frequency divider is also disclosed. When the interpolator is placed in the feedback path of a PLL, a fractional frequency multiplier/divider results.
摘要翻译：一种使用具有多相振荡器的多个相位信号的时钟源的分频器。在一个版本中，分隔器包括连接以形成环的多个点移动级。点移动阶段是在清除前一阶段的同时提升一个或零个阶段的阶段。取决于通过所有级进行点的时钟的数量级和时钟数，确定分频比。在另一个实施例中，多个锁存元件设置有分割输入，并且每个锁存元件都与多相振荡器的相位重新计时。锁存元件的输出被组合在电容器阵列中以产生输出波形。还公开了一种与分频器结合使用的内插器。当内插器放置在PLL的反馈路径中时，产生分数倍频/分频器。

9. 发明申请

WO2007109743A2 FREQUENCY DIVIDER 审中-公开
标题翻译：频率分配器
公开(公告)号：WO2007109743A2
公开(公告)日：2007-09-27
申请号：PCT/US2007/064562
申请日：2007-03-21
申请人： MULTIGIG INC. , WOOD, John
发明人： WOOD, John
IPC分类号： H04B1/00
CPC分类号： H03L7/0995 , H03K23/54 , H03K23/546 , H03L7/0998
摘要： A frequency divider using a clock source with a plurality of phase signals of a multi-phase oscillator. In one version, the divider includes a plurality of spot-moving stages that are connected to form a ring. Spot-moving stages are stages that advance a one or a zero, while clearing the previous stage. Depending on the number of stages and the number of phases of the clock to advance a spot through all of the stages, a divider ratio is determined. In another embodiment, a plurality of latch elements is provided with a divided input and each is re-clocked with the phases of a multi-phase oscillator. The outputs of the latch elements are combined in a capacitor array to create the output waveform. An interpolator useful in conjunction with a frequency divider is also disclosed. When the interpolator is placed in the feedback path of a PLL, a fractional frequency multiplier/divider results.
摘要翻译：一种使用具有多相振荡器的多个相位信号的时钟源的分频器。在一个版本中，分隔器包括连接以形成环的多个点移动级。点移动阶段是在清除前一阶段的同时提升一个或零个阶段的阶段。根据阶段的数量和时钟的相位数，通过所有级进行点，确定分频比。在另一个实施例中，多个锁存元件设置有分割输入，并且每个锁存元件与多相振荡器的相位重新计时。锁存元件的输出被组合在电容器阵列中以产生输出波形。还公开了一种与分频器结合使用的内插器。当内插器放置在PLL的反馈路径中时，会产生分数倍频/分频。

10. 发明专利

JP3536073B2 Divider 失效
公开(公告)号：JP3536073B2
公开(公告)日：2004-06-07
申请号：JP14966195
申请日：1995-05-24
申请人：アジレント・テクノロジーズ・インク
发明人：保明小松 , 吉之柳本
IPC分类号： H03L7/183 , H03K23/00 , H03K23/54 , H03K23/68 , H03L7/197
CPC分类号： H03K23/546 , H03K23/68 , H03L7/1976

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