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    • 3. 发明授权
    • Digital recording apparatus non-influenced by recording data rate and low frequency cut-off, and enhancing high frequency components of data being recorded
    • 数字记录装置不受记录数据速率和低频截止影响,并增强正在记录的数据的高频分量
    • US06804071B2
    • 2004-10-12
    • US09913246
    • 2002-02-11
    • Mamoru MizukamiKaoru Urata
    • Mamoru MizukamiKaoru Urata
    • G11B502
    • G11B20/1403G11B5/0086G11B5/09
    • Digital data recording apparatus includes a modulator for modulating a recording clock by a recording data. A reference voltage and a reference current in signal processing are set based on a reference clock having a multiple cycle of the cycle of the recording clock when the reference clock is supplied via a rotary transformer. A demodulator demodulates a modulation signal supplied via the rotary transformer to produce a demodulation signal, from which a recording signal is generated for recording on a recording medium. The demodulator obtains a modulation signal and an inverted modulation signal from which first and second saw-tooth wave signals are produced when the reference current is supplied. A mixer mixes the first and second saw-tooth wave signals, and the demodulation signal is obtained, based on the mixer output and the reference voltage.
    • 数字数据记录装置包括用于通过记录数据调制记录时钟的调制器。 在通过旋转变压器供给基准时钟时,基于具有记录时钟的周期的多个周期的基准时钟来设定信号处理中的基准电压和基准电流。 解调器解调通过旋转变压器提供的调制信号,以产生解调信号,从而从该信号产生用于记录在记录介质上的记录信号。 解调器获得当提供参考电流时产生第一和第二锯齿波信号的调制信号和反相调制信号。 混合器混合第一和第二锯齿波信号,并且基于混频器输出和参考电压获得解调信号。
    • 4. 发明授权
    • Load balancing circuit for a dual polarity power supply with single polarity voltage regulation
    • 用于双极性电源的负载平衡电路,具有单极性电压调节
    • US06778347B2
    • 2004-08-17
    • US09904721
    • 2001-07-13
    • Donald W. Janz
    • Donald W. Janz
    • G11B502
    • H02M3/155H02M2001/009
    • A load balancing circuit which operates to balance the output voltages of a dual polarity power supply with single polarity voltage regulation. The power supply outputs a positive voltage at a positive voltage with respect to a reference level and a negative voltage with respect to the reference level. The power supply further applies voltage regulation to a selected one of the positive and negative voltages and leaves the remaining one of the positive and negative voltages in an unregulated state. Positive and negative loads are coupled to receive the positive and negative voltages. The load balancing circuit detects a change in impedance of a selected one of the positive and negative loads and applies a corresponding impedance to the power supply to maintain the power supply in a nominally balanced state.
    • 负载平衡电路,用于平衡双极性电源的输出电压与单极性电压调节。 电源以相对于参考电平的正电压和相对于参考电平的负电压输出正电压。 电源进一步对正电压和负电压中的一个施加电压调节,并将正电压和负电压中的剩余电压留在未调节状态。 正和负负载耦合以接收正电压和负电压。 负载平衡电路检测正负载中所选择的一个的阻抗的变化,并向电源施加相应的阻抗以将电源维持在标称平衡状态。
    • 7. 发明授权
    • Head suspension assembly mounting nonvolatile memory and magnetic disk device
    • 头悬挂组件安装非易失性存储器和磁盘设备
    • US06707628B2
    • 2004-03-16
    • US09785283
    • 2001-02-20
    • Akira Osaki
    • Akira Osaki
    • G11B502
    • G11B5/4853G11B5/012G11B5/486G11B2005/0013
    • A head suspension assembly 4 has an arm 17 supported so as to rotate, an elastically flexible suspension 16 having one end which is fixed to an end of the arm and the other end has a magnetic head 2 mounted thereon, and a signal transmission line 18 fixed on the suspension and the arm which connects the magnetic head with a main FPC. A head amplifier 8, which transmits and receives signals to and from the magnetic head, and a nonvolatile memory 9, which stores optimized control parameters of the magnetic head and the head amplifier, are mounted together on the head suspension assembly; and, the head amplifier and the nonvolatile memory are electrically connected to the signal transmission
    • 头悬挂组件4具有被支撑为旋转的臂17,弹性柔性悬架16具有一端固定到臂的一端,另一端具有安装在其上的磁头2,信号传输线18 固定在悬架上和将磁头与主FPC连接的臂。 向磁头发送信号和从磁头接收信号的头放大器8和存储磁头和头放大器的优化控制参数的非易失性存储器9一起安装在磁头悬架组件上; 并且,头放大器和非易失性存储器电连接到信号传输
    • 10. 发明授权
    • Write-to-read switching improvement for differential preamplifier circuits in hard disk drive systems
    • 硬盘驱动器系统中差分前置放大器电路的读写开关改进
    • US06621649B1
    • 2003-09-16
    • US09709699
    • 2000-11-10
    • Hong JiangIndumini Ranmuthu
    • Hong JiangIndumini Ranmuthu
    • G11B502
    • G11B5/012G11B5/59622G11B19/04
    • The present invention relates to a preamplifier circuit comprising a plurality of amplifier stages coupled together and operable to consecutively amplify a signal associated with a head of a hard disk drive. The preamplifier circuit further comprises a power delivery circuit operably coupled to the amplifier stages and operable to provide power to the amplifier stages in a substantially concurrent manner when the hard disk drive is transitioning from a write state to a read state. In addition, the circuit comprises a control circuit operably coupled to the amplifier stages, and operable to activate at least two of the plurality of amplifier stages in a generally consecutive manner after the providing of power to the amplifier stages. In the above manner a saturation of an output of the preamplifier circuit is avoided by preventing substantially a propagation of glitches through the preamplifier circuit and providing for a substantially fast write-to-read transition time.
    • 本发明涉及一种前置放大器电路,其包括耦合在一起的多个放大器级并且可操作以连续放大与硬盘驱动器的头部相关联的信号。 前置放大器电路还包括功率传输电路,其可操作地耦合到放大器级,并且可操作以在硬盘驱动器从写入状态转换到读取状态时以大致并发的方式向放大器级提供电力。 此外,电路包括可操作地耦合到放大器级的控制电路,并且可操作以在向放大器级提供电力之后以大致连续的方式激活多个放大器级中的至少两个。 以上述方式,通过防止毛刺大量传播通过前置放大器电路并提供基本上快速的写入 - 读取转换时间来避免前置放大器电路的输出的饱和。