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    • 5. 发明公开
    • Data Center, Cooling System, and Method of Cooling Information Technology Device
    • 数据中心,冷却系统和冷却信息技术设备的方法
    • EP2293659A2
    • 2011-03-09
    • EP10173477.0
    • 2010-08-19
    • FUJITSU LIMITED
    • Katsui, TadashiIshimine, JunichiSaito, SeiichiSuzuki, MasahiroNagamatsu, IkuroOhba, YujiYamaoka, NobuyoshiUeda, AkiraUraki, Yasushi
    • H05K7/20
    • H05K7/20745
    • A data center includes a housing room (2) that nouses an information technology device (10a); an air conditioning machine (11) that cools air in the housing room (2) and supplies the air under a floor of the housing room (2); a grille (7) that allows the air supplied under the floor to circulate in the housing room (2); and a rack device (10) that houses the information technology device (10a). In the housing room (2) in the data center, the rack device (10) is arranged in such a way as to surround the grille (7). The information technology device (10a) is housed in the rack device (10) in such a way as to take in air from a space (20) surrounded by the rack device (10) via the grille (7) and discharge air to the housing room (2). The air conditioning machine (11) is arranged at a side from which the information technology device (10a) discharges air.
    • 一个数据中心包括一个安置信息技术设备(10a)的房屋(2); 空调机(11),其冷却收容空间(2)内的空气,并将收容空间(2)的地板下的空气供给; 格栅(7),其允许供应到地板下方的空气在所述容纳室(2)中循环; 和容纳信息技术设备(10a)的机架设备(10)。 在数据中心的容纳室(2)中,机架装置(10)以围绕格栅(7)的方式布置。 信息技术装置(10a)以这样的方式容纳在机架装置(10)中,即从由机架装置(10)围绕的空间(20)经由格栅(7)吸入空气并将空气排放到 房屋(2)。 空调机(11)配置在信息处理装置(10a)排出空气的一侧。
    • 6. 发明公开
    • Logic circuit
    • 逻辑电路
    • EP0226678A1
    • 1987-07-01
    • EP85309492.8
    • 1985-12-24
    • FUJITSU LIMITED
    • Takao, HisokaSato, ToshiroSaito, SeiichiHayashi, Toshinari
    • H03K19/094
    • H03K19/09443H03K19/0952
    • A logic circuit includes an inverter circuit including a first enhancement type field effect transistor (21) having a gate connected to an input and a first depletion type transistor (22) having a gate and a source which are directly connected together and to a drain of the first enhancement type field effect transistor (21); a source follower circuit including a second enhancement type field effect transistor (23) having a gate which is connected to a connecting point of the first enhancement type field effect transistor (21) and the first depletion type field effect transistor (22) and a second depletion type field effect transistor (25) having a gate and a source which are directly connected to each other and a drain which is connected to a source of the second depletion type field effect transistor (23); a circuit which supplies power to the drains of the first depletion type field effect transistor (22) and of the second enhancement type field effect transistor (25) and to the sources of the first enhancement type field effect transistor (21) and of the second depletion type field effect transistor (23); and, an output is formed at the connecting point (26) of the second enhancement type field effect transistor (23) and the second depletion type field effect transistor (25) which form the source follower circuit.
    • 一种逻辑电路包括:反相器电路,其包括具有连接到输入的栅极的第一增强型场效应晶体管(21)和具有直接连接在一起的栅极和源极的第一耗尽型晶体管(22) 第一增强型场效应晶体管(21); 源极跟随器电路,其包括具有连接到第一增强型场效应晶体管(21)和第一耗尽型场效应晶体管(22)的连接点的栅极的第二增强型场效应晶体管(23) 具有彼此直接连接的栅极和源极以及连接到第二耗尽型场效应晶体管(23)的源极的漏极的耗尽型场效应晶体管(25); 一个向第一耗尽型场效应晶体管(22)和第二增强型场效应晶体管(25)的漏极以及第一增强型场效应晶体管(21)的源极和第二增强型场效应晶体管 耗尽型场效应晶体管(23); 并且在形成源极跟随器电路的第二增强型场效应晶体管(23)和第二耗尽型场效应晶体管(25)的连接点(26)处形成输出。
    • 7. 发明公开
    • Bus transmission system
    • 总线传输系统。
    • EP0030095A1
    • 1981-06-10
    • EP80304084.9
    • 1980-11-13
    • FUJITSU LIMITED
    • Saito, SeiichiKitano, Yuji
    • H04L11/16
    • H04L12/40032G06F13/4072
    • A bus transmission system in which two or more drive circuits (TR3A, TR4A; TR3B, TR4B; TR3C, TR4C) are connected to the same line (TL), wherein both ends of a transmission line are grounded via a terminal resistance (R4A, R4C), which is nearly equal to the characteristic impedance of the line, said drive circuits have three states consisting of a low-level state in which the output impedance is small, a high-level state in which the output impedance is small and a high-impedance state in which the output impedance is very high, and when data is not to be transmitted, the drive circuits is placed in the high-impedance state, when data is to be transmitted, the high-impedance state of the drive circuits is converted into the low-level state in which the output impedance is small so that data can be transmitted based upon the low-level state and the high-level state, and when the transmission of data is finished, the drive circuits are placed in the low-level state again and thereafter are placed in the high-impedance state.