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1. 发明授权

EP2764545B1 STUB MINIMIZATION FOR WIREBOND ASSEMBLIES WITHOUT WINDOWS 有权
公开(公告)号：EP2764545B1
公开(公告)日：2018-07-04
申请号：EP12775582.5
申请日：2012-10-02
申请人： Invensas Corporation
发明人： CRISP, Richard, Dewitt , ZOHNI, Wael , HABA, Belgacem , LAMBRECHT, Frank
IPC分类号： H01L25/065 , H01L23/13 , G11C5/02 , G11C5/04 , G11C5/06
CPC分类号： G11C5/04 , G11C5/02 , G11C5/063 , G11C5/066 , H01L23/13 , H01L23/3128 , H01L23/36 , H01L23/49816 , H01L23/49827 , H01L23/49838 , H01L23/50 , H01L24/06 , H01L24/13 , H01L24/16 , H01L24/24 , H01L24/48 , H01L24/49 , H01L24/73 , H01L25/0652 , H01L25/0655 , H01L25/0657 , H01L25/18 , H01L2224/02375 , H01L2224/02379 , H01L2224/0401 , H01L2224/04042 , H01L2224/05554 , H01L2224/05569 , H01L2224/0557 , H01L2224/06155 , H01L2224/06156 , H01L2224/06165 , H01L2224/06179 , H01L2224/06181 , H01L2224/06515 , H01L2224/12105 , H01L2224/131 , H01L2224/13109 , H01L2224/13111 , H01L2224/13144 , H01L2224/13147 , H01L2224/16146 , H01L2224/16225 , H01L2224/16227 , H01L2224/24145 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48145 , H01L2224/48227 , H01L2224/4824 , H01L2224/48471 , H01L2224/49113 , H01L2224/49175 , H01L2224/73204 , H01L2224/73207 , H01L2224/73215 , H01L2224/73253 , H01L2224/73265 , H01L2225/06506 , H01L2225/06513 , H01L2225/06517 , H01L2225/06524 , H01L2225/06541 , H01L2225/06551 , H01L2225/06558 , H01L2225/06562 , H01L2225/06565 , H01L2225/06568 , H01L2225/06575 , H01L2225/06589 , H01L2924/00014 , H01L2924/01322 , H01L2924/10161 , H01L2924/1434 , H01L2924/1435 , H01L2924/1436 , H01L2924/1438 , H01L2924/15172 , H01L2924/15192 , H01L2924/15311 , H01L2924/157 , H01L2924/15787 , H01L2924/15788 , H01L2924/1579 , H01L2924/181 , H01L2924/18161 , H01L2924/3011 , H05K1/181 , H05K2201/09227 , H05K2201/10159 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/05599
摘要： A microelectronic package (100) can include a plurality of vertically stacked semiconductor chips 632, 637, the front face of at least one chip facing away from a first substrate surface (108), one or more columns (138, 143) of contacts (132) extending in a first direction (142) along surface (108). Columns (104A, 107B, 109A, 109B) of terminals (105 107) exposed at a second substrate surface (110) extend in the first direction. First terminals (105) disposed in a central region (112) of surface (110) which has width (152) not more than three and one-half times a minimum pitch (150) of the columns of terminals can be configured to carry address information usable to determine an addressable memory location. An axial plane of the at least one semiconductor chip can intersect the central region.

2. 发明公开

EP1825344A4 DATA RECEIVING APPARATUS AND CONTROL METHOD THEREOF 审中-公开
标题翻译：数据接收装置及其控制方法
公开(公告)号：EP1825344A4
公开(公告)日：2015-07-01
申请号：EP05807943
申请日：2005-10-27
申请人： SAMSUNG ELECTRONICS CO LTD
发明人： YU GYEONG-HO
IPC分类号： G06F1/04 , G06F13/40 , G11C5/06
CPC分类号： G11C5/066 , G06F13/4072

3. 发明授权

EP2290549B1 Protocol for communication with dynamic memory 失效
标题翻译：协议与动态存储器通信
公开(公告)号：EP2290549B1
公开(公告)日：2015-06-24
申请号：EP10179835.3
申请日：1996-10-18
申请人： Rambus Inc.
发明人： Barth, Richard, Maurice , Ware, Frederick, Abbot , Dillon, John, Bradly , Stark, Donald, Charles , Hampel, Craig, Edward , Griffin, Matthew, Murdy
IPC分类号： G06F13/16
CPC分类号： G11C7/22 , G06F13/161 , G11C5/066 , G11C7/10 , G11C7/1072 , G11C8/12

4. 发明公开

EP2764546A2 STUB MINIMIZATION FOR MULTI-DIE WIREBOND ASSEMBLIES WITH ORTHOGONAL WINDOWS 审中-公开
标题翻译： APPROACH尽量减少与正交WINDOWS多芯片导线连接
公开(公告)号：EP2764546A2
公开(公告)日：2014-08-13
申请号：EP12780342.7
申请日：2012-10-02
申请人： Invensas Corporation
发明人： CRISP, Richard, Dewitt , ZOHNI, Wael , HABA, Belgacem , LAMBRECHT, Frank
IPC分类号： H01L25/065 , H01L23/49 , H01L23/13 , G11C5/04 , G11C5/06 , H01L25/10 , H01L23/00 , H01L23/31
CPC分类号： G06F1/16 , G06F1/18 , G11C5/04 , G11C5/063 , G11C5/066 , H01L23/13 , H01L23/3128 , H01L23/49827 , H01L23/49838 , H01L23/50 , H01L24/06 , H01L24/16 , H01L24/48 , H01L24/73 , H01L25/0652 , H01L25/0657 , H01L25/105 , H01L2224/0401 , H01L2224/04042 , H01L2224/06136 , H01L2224/06156 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/4824 , H01L2224/73215 , H01L2224/73265 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06562 , H01L2225/06589 , H01L2225/1023 , H01L2225/107 , H01L2924/00014 , H01L2924/01322 , H01L2924/1431 , H01L2924/1434 , H01L2924/15311 , H01L2924/181 , H01L2924/18165 , H01L2924/19041 , H01L2924/19103 , H01L2924/3011 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A microelectronic package (10) can include a substrate (20) having first, second, and third apertures (26a, 30b, 30c) extending between first and second surfaces (21, 23) thereof, first, second, and third microelectronic elements (30a, 34b, 34c) each having a surface (31) facing the first surface, and a plurality of terminals (25a) exposed at a central region (23) of the second surface. The apertures (26a, 30b, 30c) can have first, second, and third axes (29a, 33b, 33c) extending in directions of the lengths of the respective apertures. The first and second axes (29a, 33b) can be parallel to one another. The third axis (29c) can be transverse to the first axis (29a). The central region (23) of the second surface (22) of the substrate (20) can be disposed between the first and second axes (29a, 33b). The terminals (25a) can be configured to carry address information usable by circuitry within the microelectronic package (10) to determine an addressable memory location from among all the available addressable memory locations of a memory storage array of at least one of the microelectronic elements (30a, 34b, 34c).

5. 发明公开

EP2454735A1 SYSTEM AND METHOD UTILIZING DISTRIBUTED BYTE-WISE BUFFERS ON A MEMORY MODULE 审中-公开
标题翻译：系统和方法分布式字节为单位的缓冲区上的内存模块
公开(公告)号：EP2454735A1
公开(公告)日：2012-05-23
申请号：EP10730021.2
申请日：2010-07-01
申请人： Netlist, Inc.
发明人： LEE , Hyun , BHAKTA, Jayesh, R.
IPC分类号： G11C5/02 , G11C5/06
CPC分类号： G06F12/00 , G11C5/025 , G11C5/04 , G11C5/066 , G11C8/12
摘要： A memory system and method utilizing one or more memory modules is provided. The memory module includes a plurality of memory devices and a controller configured to receive control information from a system memory controller and to produce module control signals. The memory module further includes a plurality of circuits, for example byte-wise buffers, which are configured to selectively isolate the plurality of memory devices from the system memory controller. The circuits are operable, in response to the module control signals, to drive write data from the system memory controller to the plurality of memory devices and to merge read data from the plurality of memory devices to the system memory controller. The circuits are distributed at corresponding positions separate from one another.

6. 发明公开

EP2306461A2 Memory with output control 审中-公开
标题翻译： Seriell verbundendeunabhängigeSpeicher
公开(公告)号：EP2306461A2
公开(公告)日：2011-04-06
申请号：EP11000195.5
申请日：2006-09-29
申请人： MOSAID Technologies Incorporated
发明人： Oh, HakJune , Pyeon, Hong Beom , Kim, Jin-Ki
IPC分类号： G11C11/4193 , G11C11/4197 , G11C16/06
CPC分类号： G06F3/0611 , G06F3/0655 , G06F3/0688 , G06F13/4243 , G11C5/066 , G11C7/1021 , G11C7/1051 , G11C7/1078 , G11C8/10 , G11C16/06 , G11C16/08 , G11C16/10 , G11C16/16 , G11C16/26 , G11C16/3459 , G11C2207/107 , G11C2216/30
摘要： An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device. In another example, a flash memory device may have a single serial data link, a single memory bank, a serial data input port, an control input port for receiving output enable signals. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices.
摘要翻译：公开了一种用于控制对半导体存储器中的串行数据链路接口的输出端口的数据传输的装置，系统和方法。在一个示例中，闪存设备可以具有多个串行数据链路，多个存储器组和控制输入端口，其使存储器件能够将串行数据传送到存储器件的串行数据输出端口。在另一示例中，闪存器件可以具有单个串行数据链路，单个存储器组，串行数据输入端口，用于接收输出使能信号的控制输入端口。闪存器件可以使用回波信号线以菊花链配置级联以在存储器件之间串行通信。

7. 发明授权

EP1395991B1 CIRCUIT INTEGRE A FAIBLE CONSOMMATION ELECTRIQUE, AYANT UNE INTERFACE DE COMMUNICATION "UN FIL" 有权
标题翻译：同时功耗更低，用电线通信接口集成电路
公开(公告)号：EP1395991B1
公开(公告)日：2010-08-11
申请号：EP01945459.4
申请日：2001-06-15
申请人： STMicroelectronics S.A.
发明人： GIOVINAZZI, Thierry , GANIVET, Filipe
IPC分类号： G11C5/06 , G11C7/00
CPC分类号： G11C7/222 , G11C5/066
摘要： The invention relates to an integrated circuit (20) comprising a binding post (11) for receiving a data-carrying electrical signal (DT) and means (CEC1) for delivering a first clock signal (CK1) consisting of clock pulses emitted after each falling edge of the data-carrying electrical signal inside a data sampling window. According to the invention, the integrated circuit comprises means (CEC2) for delivering a second clock signal (CK2) consisting of clock pulses emitted only when the data-carrying electrical signal (DT) is at the high level and data-processing means (PCC, REGB, MEM), which are synchronised by the second clock signal (CK2). Thanks to the invention, it is possible to power the integrated circuit using an electric voltage present at the binding post.

8. 发明公开

EP1981031A1 Daisy chain cascading devices 有权
标题翻译：菊花链级联设备
公开(公告)号：EP1981031A1
公开(公告)日：2008-10-15
申请号：EP08006224.3
申请日：2006-09-29
申请人： Mosaid Technologies Incorporated
发明人： Pyeon, Hong Beom , Kim, Jin-Ki , Oh, HakJune
IPC分类号： G11C5/06 , G11C7/10
CPC分类号： G11C7/10 , G06F12/0623 , G06F13/4247 , G06F13/4256 , G11C5/066 , G11C16/06
摘要： A technique for serially coupling devices in a daisy chain cascading arrangement. Devices are coupled in a daisy chain cascade arrangement such that outputs of a first device are coupled to inputs of a second device later in the daisy chain to accommodate the transfer of information, such as data, address and command information, and control signals to the second device from the first device. The devices coupled in the daisy chain comprise a serial input (SI) and a serial output (SO) , Information is input to a device via the SI. The information is output from the device via the SO. The SO of an earlier device is the daisy chain cascade is coupled to the SI of a device later in the daisy chain cascade. Information input to the earlier device via the device's SI is passed through the device and output from the device via the device's SO. The information is then transferred to the later device's SI via the connection from the earlier device's SO and the later device's SI.
摘要翻译：串联耦合设备的技术，采用菊花链级联布置。设备以菊花链级联布置耦合，使得第一设备的输出在菊花链中稍后耦合到第二设备的输入以适应信息（诸如数据，地址和命令信息以及控制信号）向来自第一设备的第二设备。耦合在菊花链中的器件包括串行输入（SI）和串行输出（SO），信息通过SI输入到器件。信息通过SO从设备输出。早期器件的SO是菊花链级联在后来的菊花链级联中耦合到器件的SI。通过设备的SI输入到较早设备的信息通过设备并通过设备的SO从设备输出。然后通过来自早期设备的SO和后面的设备的SI的连接将信息传送到更晚的设备的SI。

9. 发明公开

EP1932157A4 MULTIPLE INDEPENDENT SERIAL LINK MEMORY 有权
标题翻译：具有多个独立串行连接存储
公开(公告)号：EP1932157A4
公开(公告)日：2008-10-15
申请号：EP06790770
申请日：2006-09-29
申请人： MOSAID TECHNOLOGIES INC
发明人： KIM JIN-KI , PYEON HONG BEOM
IPC分类号： G11C11/4193 , G11C11/4197 , G11C16/06
CPC分类号： G06F3/0611 , G06F3/0655 , G06F3/0688 , G06F13/4243 , G11C5/066 , G11C7/1021 , G11C7/1051 , G11C7/1078 , G11C8/10 , G11C16/06 , G11C16/08 , G11C16/10 , G11C16/16 , G11C16/26 , G11C16/3459 , G11C2207/107 , G11C2216/30
摘要： An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device. In another example, a flash memory device may have a single serial data link, a single memory bank, a serial data input port, an control input port for receiving output enable signals. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices.

10. 发明授权

EP1830241B1 Integrated circuit I/O using a high performance bus interface 无效
标题翻译：使用Hochleistungsbusschnittstelle集成I / O电路
公开(公告)号：EP1830241B1
公开(公告)日：2008-06-25
申请号：EP06125958.6
申请日：1991-04-16
申请人： RAMBUS INC.
发明人： Farmwald, Michael , Horowitz, Mark
IPC分类号： G06F1/04 , G06F1/12 , G06F13/00 , G06F13/16 , G06F13/36 , G06F13/38 , G11C7/00 , G11C8/00 , G11C8/04
CPC分类号： G11C7/1066 , G06F11/006 , G06F11/1048 , G06F12/0215 , G06F12/0661 , G06F12/0684 , G06F13/1605 , G06F13/161 , G06F13/1678 , G06F13/1689 , G06F13/1694 , G06F13/376 , G06F13/4239 , G11C5/00 , G11C5/04 , G11C5/06 , G11C5/063 , G11C5/066 , G11C7/1006 , G11C7/1012 , G11C7/1045 , G11C7/1051 , G11C7/1057 , G11C7/1069 , G11C7/1072 , G11C7/1078 , G11C7/1084 , G11C7/22 , G11C7/222 , G11C7/225 , G11C8/00 , G11C11/4076 , G11C11/4096 , G11C29/88 , G11C2207/105 , G11C2207/108 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： The present invention includes a memory subsystem comprising at least two semiconductor devices (15, 16, 17), including at least one memory device (15, 16 or 17), connected to a bus (18), where the bus includes a plurality of bus lines for carrying substantially all address, data and control information needed by said memory devices (15, 16 or 17), where the control information includes device-select information and the bus (18) has substantially fewer bus lines than the number of bits in a single address, and the bus (18) carries device-select information without the need for separated device-select lines connected directly to individual devices. The present invention also includes a protocol for master and slave devices to communicate on the bus (18) and for registers in each device to differentiate each device and allow bus requests to be directed to a single or to all devices (15, 16, 17). The present invention includes modifications to prior-art devices to allow them to implement the new features of this invention. In a preferred implementation, 8 bus data lines and an Address Valid bus line carry address, data and control information for memory addresses up to 40 bits wide.

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