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31. 发明专利

JPS62252590A MEMORY DEVICE 失效
公开(公告)号：JPS62252590A
公开(公告)日：1987-11-04
申请号：JP9564586
申请日：1986-04-24
申请人： ASCII CORP
发明人： ISHII TAKATOSHI
IPC分类号： G06F12/00 , G06F12/02 , G06F12/04 , G06T1/60 , G11C7/00
摘要： PURPOSE:To attain a continuous serial input by providing a pair or plural pairs of memory cell arrays and data registers, while a serial input output is executed at one side of respective pairs, executing the data transferring in other side and preparing the next serial input output. CONSTITUTION:When a displaying controller 51 first makes a serial enable signal SEN into '0' and makes a signal FSB into '1', the serial system of memories 61a and 61b is stopped and an '1' signal is outputted from OR gates 66a and 66b and AND gates 62a-65a and 62b-65b are opened. The displaying controller 51 commands a reading data transfer in a row address A and the data of a row address A of memory cell arrays 1a and 1b are transferred to data registers 31a and 31b. Next, the displaying controller 51 executes the writing data transfer of the contents of the data registers 31a and 31b to a row address B of the memory cell arrays 1a and 1b, and after the transfer is completed, executes the writing data transfer of the same contents of the data registers 31a and 31b to a row address C.

32. 发明专利

JPS62192795A DISPLAY CONTROL CIRCUIT 失效
公开(公告)号：JPS62192795A
公开(公告)日：1987-08-24
申请号：JP3553786
申请日：1986-02-20
申请人： ASCII CORP
发明人： ISHII TAKATOSHI
IPC分类号： G09G1/06 , G09G1/16 , G09G1/28 , G09G5/00 , G09G5/02 , G09G5/14 , G09G5/30 , G09G5/36

33. 发明专利

JPS62174791A DISPLAY UNIT 失效
公开(公告)号：JPS62174791A
公开(公告)日：1987-07-31
申请号：JP12425886
申请日：1986-05-29
申请人： ASCII CORP
发明人： ISHII TAKATOSHI
IPC分类号： G09G5/36 , G09G1/02 , G09G1/16 , G09G1/28 , G09G5/00 , G09G5/02 , G09G5/395

34. 发明专利

JPS6250939A DUAL PORT MEMORY 失效
公开(公告)号：JPS6250939A
公开(公告)日：1987-03-05
申请号：JP19108785
申请日：1985-08-30
申请人： ASCII CORP
发明人： ISHII TAKATOSHI
IPC分类号： G11C7/00 , G06F12/00 , G11C11/34 , G11C11/401 , G11C11/41
摘要： PURPOSE:To transmit a random and serial port asynchronously by controlling the connection between a memory cell array and a serial data buffer with a write and read pointer, and controlling the connection between a data buffer and the serial data buffer with an input/output pointer. CONSTITUTION:Two data buffers 30 are provided between a memory cell array 10 and a serial port 40, and the connecting relation is controlled by a write pointer 37 and a read pointer 33. The connecting relation of the buffers 30 and a serial data buffer SDB is controlled by an output pointer 38. Here, by the level of the writable signal, the mode to read and write the memory cell is determined, and respectively, the read or write transmitting cycle signal is set. At present, a read data transmitting cycle signal is '1', then, a switch 35 is turned on, the read data are sent from the array 10. When a write data transmitting cycle signal is '1', a switch 36 is turned on, and the buffer data designated by the FF for the write pointer are sent to the array 10 by a switch 37.

37. 发明专利

JPS61283970A PICTURE DATA PROCESSOR 失效
公开(公告)号：JPS61283970A
公开(公告)日：1986-12-13
申请号：JP12579385
申请日：1985-06-10
申请人： ASCII CORP
发明人： ISHII TAKATOSHI
IPC分类号： G06T11/00
摘要： PURPOSE:To attain the development from pattern data to a color code and also to shorten the developing time to the color code without having a bit handling operation done by a CPU, by providing a color code developing circuit to which the desired information is set. CONSTITUTION:The desired information is set to a color code developing circuit 10 by a CPU and the color code is developed under the control of a timing controller 21. That is, the value obtained by subtracting 1 from the number of pattern data to be developed is set to a length counter 16 by the CPU. Then the execution signal is applied to the controller 21 and then delivered to an address bus 51 for display memory of a counter 15. While the value of a foreground register 11 or a background register 12 is selected by a selector 14 in response to the value of an upper bit of a pattern shift register 13 which holds the pattern data to be developed to a color code an then written to a display memory via a data bus 53 for display memory. Thus it is possible to perform a developing action to a color code from the pattern data at a high speed.

39. 发明专利

JPS61205018A CHATTERING ELIMINATING CIRCUIT 失效
公开(公告)号：JPS61205018A
公开(公告)日：1986-09-11
申请号：JP4595485
申请日：1985-03-08
申请人： ASCII CORP , NIPPON MUSICAL INSTRUMENTS MFG
发明人： ISHII TAKATOSHI , KANEKO MAKOTO
IPC分类号： H03K5/1254 , H03K5/01
摘要： PURPOSE:To simplify extremely the constitution and also to accelerate greatly the response with a chattering eliminating circuit, by using a flip-flop which is reset only when the output signals of each phase are turned off and set only when these output signals are turned on respectively, together with a pulse output means and a shift direction deciding means. CONSTITUTION:The X direction component output pulses MX1 and MX2 are supplied to input terminals 1a and 1b respectively; while the Y direction component output pulses MY1 and MY2 are supplied to input terminals 2a and 2b. The output signal of delay flip-flops 3 and 4 are supplied to the input terminals of the preceding value memory parts 10 and 11. The part 10 contains AND gates AN1 and AN2, an OR gate OR1 which secures an OR of the output signals of the gates AN1 and AN2 and a DFF 5 which stores the output signal of the OR1. Then the part 10 fetches the output signal value of a DFF 3 when a sampling signal Sp is active (level '1') and keeps this signal value until the signal Sp is active next.

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